Interview: Henri Richard on Rapidus, experience and ecosystem

Interviews | April 19, 2024

By Peter Clarke

2nm Node Japan Materials & processes

eeNews Europe spoke with semiconductor veteran Henri Richard who has recently been appointed general manager of Rapidus Design Solutions Inc. (Santa Clara, Calif.).

Rapidus Design Solutions is the US arm of Rapidus Corp., a Japanese startup that is building a 2nm foundry, and has been formed to engage with equipment partners and customers. Richard, has held executive positions at several leading semiconductor companies including AMD, Freescale, IBM and SanDisk, among others.

Rapidus is, in part, a Japanese government funded initiative to get the country back to chip manufacturing at the leading edge for national strategic reasons. This is a task that will be complex, time-consuming and expensive, without any guarantee of success.

Richard started the interview by saying: “Everything is on-time and on-schedule.”

Rapidus has broken ground at the selected site for its wafer fab in Chitose City, Hokkaido. The wafer fab is called IIM-1 with IIM standing for Innovative Integration for Manufacturing (see Rapidus breaks ground on 2nm fab, goes on hiring spree).

Rapidus has already hired more than 200 employees and has dispatched many of these to the Albany Nanotech Complex in New York to work with IBM researchers to develop the technologies for the production of 2nm logic semiconductors. The partnership to use IBM’s semiconductor intellectual property is a fundamental part of the plan (see Rapidus seeks billions of dollars to use IBM’s 2nm process).

Time to test

“Testing will be done in Albany on both the technology and on chips. The process will transfer to Hokkaido in 2026 for production in 2027,” Richard told eeNews Europe. However, Richard was not prepared to discuss the technology, or what test chips being made.

When first announced in May 2021 IBM’s 2nm process was shown to include three gate-all-around (GAA) nanosheet channels in each fin. Extreme ultraviolet (EUV) processing is necessary to define the small dimensions in the process but it allows nanosheet widths of between 15nm and 70nm. In an echo of IBM’s earlier work as a pioneer of silicon-on-insulator (SOI), the process included a bottom dielectric isolation to enable 12nm gate length. The process was said to support multiple threshold voltages for both SoC and high-performance computing applications. However, it was not clear how much strain engineering was present or whether novel materials were used in the transistor channels (see IBM announces first 2nm chip and manufacturing process).

Typically, logic process development involves a series of test structures. These progress from defining individual transistors to flip-flops, logic gates and SRAMs. The next stage would involve the definition of standard cell libraries that systematize how logic is laid out across of rows of transistors. Moving up in complexity would take test chips to memory arrays and I/O interfaces and pads. This in turn should allow the creation of relatively complex logic chips. In Rapidus’ case this could be a RISC-V processor, or a design of processor provided by IBM, which can be tested for its ability to run software and provide key yield figures and indicate where further optimization is required.

As IBM’s 2nm process is based on EUV lithography, much of this work has to be done as an iterative co-optimization with design closure and such things as optical proximity correction (OPC). OPC compensates for image errors that occur due to diffraction or process effects related to lithography. It does this by moving edges or adding extra structures to the pattern written on the photomask. At the leading-edge, OPC makes use of machine learning models which can be trained to predict optimal mask patterns.

Rapidus and experience

Established foundries such as Samsung, TSMC and Intel have a continuous history of manufacturing. Lessons learned at each node have been carried forward as baseline knowledge for the next node. In contrast Rapidus is a startup, has a steep learning curve to climb and its partner IBM is not a commercial manufacturer of chips.

Could this be a major problem to Rapidus?

“There is a tremendous amount of learning that comes from each successful node,” Richard said. But he argued that for Rapidus the situation is manageable. “A lot of knowledge is held in the ecosystem, in the chip manufacturing equipment makers and EDA companies and so on. We also have the advantage of not being encumbered with history.”

“That means that at IIM we can run the fab in a different way to some competitors, a different approach which can achieve significant improvements in cycle time,” Richard said. Certainly, the fact that advanced logic chips can spend six months or more in foundry wafer fab is problematic when introducing a chip to the market. A significant improvement could provide a differentiator and be welcomed by customers who do not need high volumes.

Everybody loves Rapidus

Richard said that Rapidus improvements would be related to tool layout and transportation systems, but did not explain further. A flow based on individual wafers rather batch processing might provide such a scheme.

Richard said that one of the big advantages Rapidus has is the fact that the market and many national governments are eager for alternative sources of leading-edge chips.

Richard says that when Rapidus was launched it recloned it was looking to take part in a US$80 billion annual market opportunity. With the subsequent rise in demand for advanced logic chips, spurred by AI, it is more like a US$150 billion annual opportunity, Richard said.

Richard pointed out that TSMC is sold out at the leading edge – busy serving relatively few very large customers – while Samsung is not a pure-play foundry and could compete with customers in some application sectors. “There is a need for alternative sources and everyone in semiconductors wants Rapidus to succeed. It relieves the pressure and Japan is a strong ally of the US,” Richard said.

Roadmaps and chiplets

To appeal to potential customers Rapidus will also need to build confidence that it will be around beyond the 2nm node and can address considerations such as packaging. It is notable that Intel has 18A and 14A (nominally and approximately equivalent to 1.8nm and 1.4nm) manufacturing processes scheduled for production by the time Rapidus is meant to be introducing its 2nm process.

We asked Richard if Rapidus has a roadmap to go beyond 2nm. Richard confirmed there is a phase two that will take Rapidus down in geometry but would not provide a timetable. For now Rapidus is focused on its primary deliverable, a viable 2nm manufacturing process for advanced logic. “We need a handful of good customers to ramp the fab,” he said.

We asked Richard how Rapidus would address such issues as packaging and chiplet-based components.

While there are standard ways of transferring wafers to independent package and test companies the situation is somewhat different when bringing chiplets from multiple wafers to be attached to interposer layers and then packaged. This is often captive and often proprietary or at least not standardized. However, it is notable that some independent chiplet packaging houses are being formed, such as Silicon Box (see Silicon Box to build €3.2 billion Italian chiplet factory).

Richard’s response: “Part of the money is about the back-end. The back-end is going to be as important as the front-end. It is a bit early for us to talk about that. Certainly, an ecosystem is an important part of success,” said Richard.

That is true not just for packaging but also more broadly and a key to success for Rapidus.