InvenSense, NTT join Singapore’s MEMS consortium

InvenSense, NTT join Singapore’s MEMS consortium

Business news |
By Peter Clarke

Singapore’s Institute of Microelectronics (IME) has formed two consortia to help with this process and leverage its research expertise in MEMS, photonics and packaging. The first is a consortium of nearly a dozen manufacturers – from InvenSense and Corning to Fraunhofer and NTT – has pledged to meld MEMS and photonics before the end of the decade.

“The Internet of Things will drive sensor growth to trillions of units as sensors become a fundamental economic driver. Disruptive sensor applications are expected to change our lives. Materializing these huge business opportunities requires a paradigm shift in sensor innovation and manufacturing.” Mo Maghsoudnia, vice president, technology and worldwide manufacturing at InvenSense told EE Times. “IME’s packaging consortia partnership will allow us to identify and develop MEMS packaging innovative solutions in order to scale up for the IoT.”

Silicon grating coupler: 2D grating to achieve polarisation diversity performance; Grating coupler with silicon overlay to reduce the coupling loss (<2.6 dB) on 220- nanometer (nm)-thick Silicon on Insulator (SOI). Source: IME.

The Singapore-based Agency for Science, Technology and Research (A*STAR) has commissioned its Institute of Microelectronics (IME) to form two consortia, first the MEMS and Photonics Consortium. So far their ranks include Delta Electronics Inc., InvenSense Inc., Standing Egg Inc., STATS ChipPAC Ltd, ULVAC, Inc. The second consortium is the Silicon Photonics Packaging Consortium consisting of Accelink Technologies Co., Ltd., Corning Inc., Fujikura Ltd., Fraunhofer Heinrich Hertz Institute and NTT.

The Silicon Photonics Packaging Consortium is now entering its second phase (see figures for progress already made in the first stage) but the MEMS consortium is just getting kicked off, pledging to fully integrate heterogeneous MEMS+Photonic devices into the same package using what was originally called the Nasiri Process ( ). The Nasiri Process caps the MEMS chip with its own application specific integrated circuit (ASIC, here containing the silicon photonics) thereby hermetically sealing the stacked die at the wafer scale without requiring space-consuming wire bonding or through-silicon vias (TSVs). This cavity-capping process is being enhanced by IME’s novel metal deposited silicon pillars as through-mold interconnects. The technique will be adapted to timing devices, inertial sensors, and radio frequency (RF) MEMS packaging.

The result, according to the consortia, will be higher-power efficiency and lower costs for both the MEMS and silicon photonic parts of the heterogeneous silicon stacked-die components.

The MEMS Wafer Level Chip Scale Packaging consortium and Silicon Photonics Packaging Consortium together will cooperatively approach the melded MEMS+Photonics goal. The consortia will also leverage IME’s portfolio of already developed design, fabrication, wafer-level and silicon photonics packaging expertise.

Precision fiber groove formation. Source: IME.

Besides IoT devices, from wearables to smartphones to tablets, the IME consortia will also aim for markets serving network infrastructure and wireless communications using unconventional “non-digital” mechanical and photonic based innovations, according to IME.

Silicon photonics with higher broadband wireless communications speeds and bandwidth, higher density interconnects and optical components that outperform electronic components will also be a goal of the consortia, according to IME.

Starting with the device libraries and toolboxes already developed in phase one of the Silicon Photonics Packaging Consortium, the second phase will cooperatively develop low-profile lateral fiber assemblies, laser diodes and associated photonic components along with the MEMS Wafer Level Chip Scale Packaging Consortium.

Already the Silicon Photonics Packaging Consortium has demonstrated a laser welding technique for photonic components with less than 1.5 decibel (dB) packaging loss and less than 8 dB total fiber-to-chip-to-fiber loss, all built in silicon. The Consortium plans to develop even lower loss silicon coupling modules to laser diodes along with the thermal models necessary to match high-data bandwidth with the thermal dissipation and assembly margins for low cost.

The consortium aims to reduce the form factor of integrated MEMS and ASICs by approximately 20 per cent, as well as lower manufacturing costs by approximately 15 per cent. These cost-effective packaging solutions are also aimed at producing better electrical and reliability performance.

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