IP builds a MIPS cpu optimised for safety-critical systems design

IP builds a MIPS cpu optimised for safety-critical systems design

New Products |
By Graham Prophet

The release is of a highly-scalable 64-bit MIPS multiprocessing solution that has been stringently assessed and validated to meet functional safety (FuSa) compliance for ISO 26262 and IEC 61508 standards, for use with the compute-intensive tasks in emerging safety-critical systems such as autonomous vehicles, industrial IoT and robotics. Imagination claims it surpasses the capabilities of other FuSa CPU IP cores; the I6500-F provides a high-performance, highly efficient backbone for the many-core designs that drive these systems, scaling to 64 heterogeneous clusters of multi-threaded multi-core MIPS CPUs and other accelerators in a system.


FuSa is essential to all parts of a safety-critical system, and that includes the CPU IP at the heart of the SoC. Applications such as autonomous vehicles and industrial control systems in smart factories require ever-increasing levels of processing that exceed the capabilities of today’s FuSa compliant CPU IP cores. Engineers can use the extended performance capability of the I6500-F to efficiently integrate increased intelligence – including AI techniques such as CNNs and DNNs – in their safety-critical devices.


Imagination is implementing fundamental safety technologies across the MIPS portfolio, building on existing work with IP cores including the MIPS P5600, which is being used in a safety critical design with redundancy for a high-reliability industrial environment.


It also continues Imagination’s safety collaboration with Mobileye. Mobileye’s EyeQ4 SoC for ADAS uses MIPS interAptiv and M5150 CPUs with software self-core test, designed for ASIL B. Its next-generation EyeQ5 SoC for autonomous vehicles is based on the I6500-F CPU and will be manufactured in 7-nm FinFET. EyeQ5 will be an open software platform on which customers can deploy their own algorithms – a capability facilitated by MIPS architectural elements including hardware virtualization. Mobileye SoCs are already available in ADAS systems today.


Elchanan Rushinek, SVP engineering of Mobileye, says: “Our EyeQ5 SoC will be the most advanced solution of its kind for fully autonomous vehicles which will start rolling out in 2020. The ASIL B(D) features in the I6500-F are key to ensuring our chip achieves the highest level of safety. Full cache coherency between CPUs and vision accelerators in the I6500-F makes it an ideal platform for heterogeneous compute, and unique features such as inter-thread communication add to the real-time capability.”


Imagination has established design and safety methodology and processes with documented evidence based on ISO 26262 requirements including safety planning, verification reviews and confirmation measures.


The I6500-F is designed to meet requirements for ASIL B(D) level, allowing the I6500-F to target demanding automotive applications up to ASIL D. The IP was developed as a Safety Element out of Context (SEooC) with a safety lifecycle based on a close collaboration with lead partners and together with a common independent safety assessor, ResilTech S.r.l. The I6500-F design safety lifecycle aligns closely with the component vendor safety lifecycle, based on ISO 26262, 2011 1st Edition standard but already considering best practices for IP from Part 11 to be present in the 2nd Edition of ISO 26262 and already available in the published DIS version.



I6500-F to FortifAI intelligent systems
The I6500-F represents, Imagination adds, a new class of MIPS processors designed to ‘FortifAI’ next-generation intelligent systems – delivering extremely high system efficiency and scalable computing and raising the bar on functional safety.


The MIPS I6500-F builds on the MIPS I6500 CPU, a 64-bit, multi-threaded, multi-core, multi-cluster CPU that is scalable from embedded to cloud. Both IP cores can coherently implement optimized configurations of CPU cores within a cluster (‘Heterogeneous Inside’) and a variety of configurations of CPU clusters and GPU or accelerator clusters on a chip (‘Heterogeneous Outside’). With features including Simultaneous Multi-threading (SMT) and hardware virtualization (VZ), the IP offers a range of benefits including “zero context switching” for applications requiring real-time response. It is also OmniShield-ready, providing a strong foundation for security-by-separation.


The QMS based development process that addresses systematic failures is the foundation of the MIPS I6500-F. Support for run-time LBIST and extensive use of redundancy across critical registers and embedded memories throughout the cores enables detection of transient and permanent faults. Redundancy is extended within the Coherence Manager (CM3) and IO Coherence Unit (IOCU) to complete the protection throughout the MIPS I6500-F multi-core cluster.





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