IP builds low-power floating point core for connected devices
Cortus (Montpellier, France) designs silicon-efficient, 32-bit processor IP: the FPS26 single precision floating point IP core is the third in a family of products based on the Cortus v2 instruction set. The core is aimed at embedded systems requiring good floating point computational performance while also delivering small silicon area and low power dissipation.
Cortus licenses a range of low power 32-bit processor cores for intelligent connected devices. With growing numbers of controllers in solar energy and industrial control requiring floating point algorithms, many applications require floating point operations executed in hardware to achieve their performance goals. Complex matrix inversion is a challenging computation in MIMO (multiple-input and multiple-output) wireless systems due to challenges around precision, quantisation and scaling which can be mitigated by using floating point.
“For companies developing intelligent ‘things’ requiring floating point algorithms, our FPS26 core offers outstanding computational performance while efficiently using silicon area”, says Michael Chapman President & CEO of Cortus. “It is an excellent fit with the industrial internet of things and with power control applications”.
Although historically (Cortus adds) embedded software has been dominated by fixed-point operations, there are cases where values may have large dynamic ranges and floating point computation is required or advantageous. Examples include matrix inversion in MIMO baseband processing, matrix multiplication and fast Fourier transforms (FFTs).
The FPS26 has a Harvard architecture, sixteen 32-bit registers and a 5-stage pipeline. It offers an IEEE 754 single precision hardware floating point unit, a pipelined parallel multiplier and a hardware divider. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The small size of FPS26 makes it suitable for cost sensitive applications. The CPU starts at around 0.192 mm² using a 90 nm technology. Using the Linpack benchmark FPS26 delivers 9.7 times better floating point performance than the APS25 integer core.
Up to eight co-processors can be added to an FPS26 core. The Cortus coprocessor interface allows licensees to add custom coprocessors, for example to accelerate computations in cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.
All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium uC/OSII, Micrium uC/OSIII & TargetOS.
Cortus S.A.S.: www.cortus.com
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