IP builds USB 2.0 Device Controller with ULPI interface

IP builds USB 2.0 Device Controller with ULPI interface

New Products |
By Jean-Pierre Joosting

The core contains USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. It supports 12 Mb/sec “Full Speed” (FS) and 480 Mb/sec “High Speed” (HS) serial data transmission rates. Tomek Krzyzak, VP of DCD addresses the question, “why not USB 3.0?”; he comments, “honestly speaking in 99.9% of embedded applications, USB 2.0 is more than enough.”

The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

DCD’s USB IP Core portfolio includes also: Audio Platform USB 2.0 – Audio Devices Design Platform, USB 2.0 HID Platform – USB 2.0 Human Interface Devices Design Platform, USB 2.0 MS Platform – USB 2.0 Mass Storage Devices Design Platform, USB 2.0 DUSB2 – USB 2.0 Device Controller USB 2.0 (UTMI interface).


next page; feature list

Key features:

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Software configurable EP0 control endpoint size 8-64 bytes
  • Software configurable 15 IN/OUT endpoints:
  • configurable number of endpoints
  • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
  • configurable direction of each endpoint
  • configurable size of each endpoint: 8-1024 bytes
  • Supports ULPI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Scan test ready
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