IP characterization throughput speed increase by a factor of 2 to 3
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By optimizing the size of these cell packets, job queuing overhead is greatly reduced, optimizing the use of multi-CPU cores that use shared memory. Throughput is further improved by enabling multi-threading for the simulations within each packet, conserving both memory and CPU resources for each machine.
Multiple distinct packets utilize all available memory and CPU threads simultaneously, resulting in a highly efficient usage of compute resources and providing up to 3X improvement in throughput. The new packet method is particularly well-suited to the large cell libraries used by leading IP providers, foundries and semi-conductor firms that may contain as many as 6,000 cells.
Liberate is an ultra-fast library creator that generates electrical models in Liberty, Verilog, Vital and IBIS formats. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models) Liberate also supports ultra-low power and high speed design styles that include power gating cells, state retention registers, level shifters, pulse clocking and CML.
Variety creates SSTA models for PrimeTime VX, Extreme GoldTime and Cadence ETS that include the impact of process parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances.
Both linear and non-linear models can be created as well as driver and receiver current source models, both Composite Current Source (CCS) and Effective Current Source Models (ECSM) are supported. Variety can characterize for both global (systematic) and local (random) variation. Variety also creates AOCV (Advanced On Chip Variation) tables to support non-statistical timing flows.
Visit Altos Design Automation at www.altos-da.com
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