IP Core for smart card reader apps
DSMART is a fast, versatile and cost-competitive IP Core intended for smart card reader applications. It’s been designed to combine highly reduced CPU utilisation and low area consumption, and to be able to activate and deactivate cards, perform resets, handle ATR reception and many additional features.
The DSMART is a configurable IP Core, so it can be easily adjusted to the project’s needs. Data transfer to and from the host system can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensures the exact result, no matter which convention it encounters. Elementary Time Unit (ETU) – time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides a non-gated clock with a wide range of possible frequencies.
The IP Core implements also a special power down mode, in which the card clock is held in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention-independent result. The received CRC/LRC is not stored in the FIFO, so it can be read in case of CRC/LRC error. The DCD IP Core also provides an optional block length counter to secure the DMA block transfer and automatic CRC/LRC.
Key features are;
Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
Support for asynchronous Smart Cards
Dual configurable length FIFO with two programmable thresholds
Card detection input
Software-configurable interrupts
Automatic convention detection and decoding
Programmable non-gated card clock generator
Automatic ETU generator
DMA support for transmit and receive
Hardware CRC and LRC calculations
Card power down mode with clock stop high and clock stop low possibility
Special fast block mode for T1 protocol (optional)
CRC/LRC hardware generation and checking
Byte counter with automatic CRC/LRC affixing(optional)
No inertial tri-state buffers
Fully synchronous synthesisable design
DCD; https://dcd.pl/ipcore/884/dsmart/
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