IP cores enable video bridging functions in FPGA
The IP is for the CrossLink FPGA range, that Lattice designed to address barriers faced by the increasingly complex and dynamic video market. The latest cores include:
– CSI-2/DSI D-PHY Receiver – Converts MIPI CSI-2/DSI data streams to parallel data
– CSI-2/DSI D-PHY Transmitter – Converts parallel formatted data streams to MIPI CSI-2/DSI
– FPD-LINK Receiver – Converts FPD-LINK video streams to pixel clock domain
– FPD-LINK Transmitter – Converts Pixel Data Streams to an FPD-LINK video stream
– SubLVDS Image Sensor Receiver – Converts SubLVDS image sensor video stream to pixel clock domain
– Pixel to Byte Converter – Converts pixel format data to parallel byte format for D-PHY transmitter
– Byte to Pixel Converter – Converts parallel byte format from a D-PHY receiver into pixel format
Lattice has also included a 1:2 MIPI DSI Display Interface Bandwidth Reducer, which utilizes select modular IP cores above to bridge an input video stream into two streams or one lower resolution stream.
Lattice comments that the mobile industry demands cost-effective devices that bridge between MIPI and other traditional or legacy display and camera interfaces. “Our customers are asking for FPGAs with MIPI D-PHY capability to solve increasingly difficult video interface problems. Too often, they reach barriers with solutions that miss the mark on power efficiency, size and performance,” said Tom Watzka, product marketing manager at Lattice Semiconductor.
The expanded suite of CrossLink IP cores is available in the Clarity Designer tool in Lattice’s Diamond software.
Lattice; www.latticesemi.com / www.latticesemi.com/CrossLink
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