IP provides Compute Express Link for chip designers.

IP provides Compute Express Link for chip designers.

New Products |
By Ally Winning

PLDA is now perfectly positioned within the IP arena to provide both CXL and Gen-Z technologies to designers in the semiconductor space, including in datacenter, storage, compute, AI, and networking industries. CXL and Gen-Z are complementary high speed interconnect protocols, with CXL enabling cache coherent node-level computing and Gen-Z focusing on fabric connectivity at the rack and row level. PLDA’s announcement of the XpressLINK CXL IP combined with the company’s upcoming Gen-Z IP furthers the aims outlined in the MoU announcement and ensures early adopters have the opportunity to integrate these solutions seamlessly into their designs. PLDA remains committed to both protocols and is actively participating in various workgroups to accelerate adoption and ensure interoperability.

The XpressLINK CXL IP is a parameterizable Compute Express Link (CXL) Soft IP controller designed for both ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA’s silicon-proven XpressRICH Controller for PCIe 5.0 architecture for, and adds CXL.cache and CXL.mem specific to CXL.ç


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