IP takes ‘legacy’ 68HC08 architecture to 100million instructions/sec
Digital Core Design’s DF6808, even in standard configuration, offers integrated on-chip major peripheral functions. But, according to the company’s CEO Jacek Hanke it’s just the beginning: “The DF6808 MCU Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and the Synchronous Serial Peripheral Interface (SPI)”. To enable even more functionality in design, the main 16-bit, free-running timer system, has two input capture lines and two output-compare lines.
The DF6808 has been equipped with proprietary safety functions, which speed the design process. To protect against system errors, self-monitoring circuitry has been included on-chip. The Computer Operating Properly (COP) watchdog system, protects against software failures. And an illegal opcode detection circuit provides a non-maskable interrupt, once the illegal opcode occurs.
Two software-controlled power-saving modes – WAIT and STOP are available to conserve additional power. These modes make the DF6808 IP Core attractive for automotive and battery-driven applications.
The DF6808 is fully customisable, and can be delivered in the exact configuration to meet target design requirements, with no unused features and wasted silicon. DCD’s IP Core includes a fully automated test bench with complete set of tests, for package validation at each stage of the SoC design flow.
The DF6808 has a built-in support for DCD Hardware Debug System called DoCD, a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCD enables non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, user defined peripherals, data and program memories.
DF6808 CPU features include;
FAST architecture – 3.2 times faster than the original implementation
Software compatible with 68HC08 industry standard
Configurable Harvard or Von Neumann architectures
11 times faster multiplication
64 bytes of System Function Registers space (SFRs)
Up to 64K bytes of Data Memory
Up to 64K bytes of Code Memory
De-multiplexed Address/Data Bus to allow easy memory connection
Two power saving modes: STOP, WAIT
Ready pin allows Core to operate with slow program and data memories.
Fully synthesisable
No internal reset generator or gated clock
Positive edge clocking and no internal tri-states
Scan test ready
800 MHz of virtual clock frequency compared to original implementation
DCD (Poland); https://dcd.pl/ipcore/113/df6808/
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