IP to simplify power mode transitions in SoC designs

IP to simplify power mode transitions in SoC designs

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By eeNews Europe

Battery life with ever more feature-packed applications requires ultra low-power optimisation to reduce overall power consumption. Reaching the low-power consumption target in an SoC implies, Dolphin says, both aspects of:

Turning on and off different functions through clock gating and power-gating techniques for implementing power domains; and, managing the transitions between modes of these power domains

With its Maestro offering, Dolphin says it has rendered straightforward, this previously complex task for SoC integrators. It facilitates the design of the Activity Control Unit (ACU) or Power Management Unit (PMU Logic) and serves to manage power island modes and mode transitions whatever the complexity of the SoC.

The Maestro network relies on different principles:

– Smart combination of soft and hard modules which structure and simplify the hierarchical design of the ACU or PMU Logic

– More flexible and reusable than a custom “hand-made” interconnection and faster development than a full C/C++ solution

– Application of the principle of subsidiarity which eliminates the risk of “conflict of modes” between shared power regulators and clock generators

A dedicated control bus is used, that is independent from the functional buses, thus authorising the construction of the power island architecture over the functional block architecture. As well as Maestro, Dolphin offers optimisation of power management networks to the DELTA standard.

Dolphin Integration;

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