MENU

ISO 26262 arrives at chip design level

ISO 26262 arrives at chip design level

Technology News |
By Christoph Hammerschmidt



ISO 26262 has been in existence for about ten years. As the authoritative standard, it regulates the processes involved in the development of electronic systems in cars and ensures the functional safety (FuSa) of these systems. Until now, this standard was primarily applied at the system level. Because increasingly complex SoCs with heterogeneous multi-core architecture are taking on ever more extensive safety-relevant tasks in automotive electronics, Cadence sees the need to extend these development processes to the chip design level as well. To this end, the company has developed a comprehensive software platform that is not only intended to accelerate development while incorporating security aspects, but also to provide essential support in the complicated ISO 26262 certification process. Similar to ISO 26262 in the automotive sector, the new Cadence Safety Solution also supports Functional Safety in the field of mechanical engineering and automation, where the IEC 61508 standard is applied. The same applies to the corresponding safety standards in aerospace engineering.

Besides this more technical reason, there is a second reason for integrating the automotive safety standard into chip design: more and more car manufacturers and suppliers want to build their chips themselves, such as Tesla.

But there are also reports from companies such as Volkswagen and Mercedes-Benz that they want to reduce their dependence on external suppliers by building these increasingly strategic components. “We are seeing enquiries from industry sectors that were previously unthinkable,” confirms Robert Schweiger, Director, Automotive Solutions at Cadence. And of course, Cadence is also addressing its regular customers with the software – semiconductor companies that manufacture products for safety-relevant vehicle components at the chip level.

The Cadence Safety Solution includes support for both analogue / mixed-signal circuits and digital ICs. It covers the spectrum of so-called FMEDA (Failure Modes Effects and Diagnostic Analysis) functions. This means that it enables users to carry out a comprehensive weak point analysis as well as the targeted injection of errors for test purposes. It enables early investigation of functional security architectures as part of the chip development process and uses native chip design data to efficiently perform accurate security analysis. Machine learning algorithms are also used in this process. In addition, these functions can also be used to optimise chip designs.

The Cadence Safety Solution includes new verification tools such as the Midas Safety Platform, the vManager Safety Manager and the Xcelium Safety Simulator. In addition, the Safety Solution includes existing verification, design, analogue and digital tools, such as the JasperGold Functional Safety Verification (FSV) App, Legato Reliability Solution, and Spectre Simulation Platform, among many others. With integrated defect campaign management, users can achieve a reduction in turnaround time by a factor of 3, Cadence promises.

To bring the aspect of functional safety into chip design, the standardisation organisation Accellera has developed the Unified Safety Format (USF), which enables the automation of the corresponding analyses and optimisations. Based on the existing Unified Power Format, USF provides access to Cadence’s extensive chip database, including chip IP blocks. In addition, the chip design data can be linked with the foundries’ production data. According to Schweiger, this makes it possible to estimate possible manufacturing errors.

With the networking of vehicles and the advance of software-based functions, another challenge is facing the developers of vehicle chips: cyber security. “These two topics are closely related,” confirms Schweiger. “Because without cyber security, functional security is also not possible.” Cadence has also taken this topic into account, for example in the Jasper verification tool. But separate security apps are also available. This enables users to prove whether specified signals and I/O processes can be affected by cyber problems or not. However, development in this area has not yet progressed too far – “the flow for functional safety is already further developed than that for security,” concedes Schweiger. Here, users can hope for new impulses in the future.

Early adopters such as automotive chipmaker Melexis already had their first experience with Cadence’s functional safety software. “In our Automotive SoC functional safety flow, we achieve ISO 26262 compliance by running fault analog simulations with customizable rules for optimized distribution, sampling size, monitoring and safety criteria,” describes Melexis design engineer Yurii Toporov. “We use the Cadence Legato Reliability Solution to perform fault injection into our analog designs, run simulations and incorporate the results into our safety metrics. The solution integrates well with the Virtuoso platform, allowing us to reuse the testbenches and simulation environment setup. With this solution, we are able to meet ISO 26262 safety requirements with the necessary accuracy and flexibility with high productivity.”

www.cadence.com

Related articles:

Safety-critical ISO26262 ASIL D certification for static analysis tool

Fast track to ISO 26262 ADAS chips with built-in functional safety

Integrity RTOS brings functional safety to RISC V

Static code analysis suite is FuSa certified

Consolidation will change the automotive chip industry says Yole

Fraunhofer zooms RISC-V into the functional safety zone

Consolidation will change the automotive chip industry says Yole

 

 

 

 

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

Linked Articles
10s