The prototype’s 96 computing cores are organized in six chiplets, each made in 28nm FDSOI manufacturing process and which are 3D-stacked in a face-to-face configuration using 20-micron pitch micro-bumps onto an active interposer embedding through-silicon vias (TSVs) in a 65nm technology node.
The interposer integrates: voltage regulators, a memory I/O controller and the physical layer for socket communication. The design was performed using a 3D CAD tool from Mentor Graphics on the STMicroelectronics process.
The overall system architecture offers a scalable distributed cache-coherent architecture between all the chiplet computing tiles, which are interconnected through the active interposer. The innovative cache-coherent architecture allows easy software deployment through a hierarchy of caches, for full system scalability up to 512 cores, Leti said.
It was not immediately disclosed whether these were ARM cores, RISC-V cores are some other proprietary processor core.
Future work will address die-to-wafer hybrid bonding technology, which offers denser 3D interconnects with better electrical, mechanical and thermal parameters. For the longer term, Leti is investigating photonic-interposer technology as a 3D-based photonic chiplet approach, offering low-latency, high-bandwidth, energy-efficient photonic communication.
Cross-section of interposer-chiplet assembly. Source: Leti.
The work was presented on February 17 at ISSCC 2020 in the paper, “A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2 @ 82%-Peak-Efficiency DC-DC Converters.”
Pascal Vivet, lead author of the paper, said active interposer technology will be an enabler of integrated heterogeneous functions. He added that chiplet-based ecosystems would now be rolled out rapidly in the high-performance computing sector and others such as automotive.
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