ISSCC: Terabit memories and compute-in-memory SRAM
ISSCC opens formally on Monday February 17 at the Marriot Marquis hotel in downtown San Francisco. We commend fourth keynote speaker Dario Gill, Director of IBM Research who is going to talk about the future of computing, which he describes as “Bits plus Neurons plus Qubits.” He makes it clear in the abstract that the future of computing is going to be very different to a past that was created by cheaper and cheaper bit processing.
And in high performance machine learning session paper 7.2 is notable for its high performance of 825TOPs and because it comes from Alibaba – or perhaps the PingTogue subsidiary of Alibaba. “A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS” is credited to Alibaba researchers around the globe.
There will be numerous 7nm processors from Samsung and AMD but it is also notable that AMD will discuss its “Chiplet Architecture for High-Performance Server and Desktop Products” in paper 2.2 while CEA-Leti will discuss “220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters” in paper 2.3.
The non-volatile memory section grabs the attention with two papers on 1Tbit memories. Paper 13.1 comes from Samsung and describes a 4bit per cell NAND flash memory. It is not clear whether this is a planar design or stacked but no mention is made of 3D stacking.
Paper 13.2 from SK Hynix is “A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique.”
Next: TSMC migrating MRAM
In the following paper it is notable that TSMC reports in the migration of its spin-torque transfer MRAM to 22nm. TSMC had plans to enter so-called “risk production” of both embedded MRAM and embedded ReRAM in chips in 2019 using a 22nm manufacturing process (see Report: TSMC to offer embedded ReRAM in 2019). This 32Mbit modules has a 10ns read time, 1 million cycles endurance, and 10 years data retention at 150 degrees C.
In session 15 on SRAM TSMC reports one of the first benchmarks for its 5nm process “A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.”
In paper 15.3 TSMC reports on a 7nm compute-in-memory SRAM macro for machine learning applications. This macro-cell is capable of supporting 372.4 GOPS performance and achieving well in excess of the 100TOPS/W efficiency touted by others for the compute-in-memory approach.
On the sensors front Samsung, not known for MEMS manufacturing but well known for its mobile phones, will report on an integrated electronic nose with four embedded gas sensors, a temperature sensor and a relative humidity sensor. The sensor measures 4.0mm by 3.7mm by 1.0mm deep.
The final recommendation is from ARM researchers who present a microcontroller processor with a 10nW sleep mode which should surely be a boon for IoT. Paper 27.2 presents “M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power.”
Related links and articles:
News articles:
ISSCC: Intel adds embedded ReRAM to 22nm portfolio
Report: TSMC to offer embedded ReRAM in 2019
Startup proposes special SRAM for AI
ST, FDSOI lead machine learning spike at ISSCC
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