It’s crunch time (again) for EUV lithography

Technology News | July 6, 2015

By eeNews Europe

Materials & processes

Reducing costs per transistor at the next-generation, the 10nm node, will be tricky. Even more challenging will be getting extreme ultraviolet lithography ready to enable a full 7nm node.

Further out, scaling to and beyond the 5nm node may require a whole new kind of chip technology. Increasingly experts speculate the answer will emerge as some sort of stacking that is not yet on the whiteboard.

The mid-term challenges are currently the most pressing. The 7nm process will be an expensive half node if the long delayed extreme ultraviolet lithography systems are not ready for early production in 2017.

Researchers here are upbeat EUV will arrive in time, but there are plenty of challenges ahead:

The light source needs an upgrade to at least 180W, up from today’s best demo of 110W at ASML.
The systems need to be available at least 80% of the time, up from an average of about 50-60% today.
Systems need to increase throughput from 70-80 wafers per hour to something closer to the 200 w/h of today’s immersion steppers.
Resists need to be more sensitive to work at lower doses with less rough edges.
New protective wafer covers, called pellicles, may need to be designed to replace the initial pellicle ASML is now supplying its customers for use at the relatively low 80-110W power levels.
Improvements are needed in finding and fixing defects.

"We are confident EUV will enter manufacturing most likely starting at the 7nm node," Luc Van den Hove, chief executive of Imec said at a press conference here.

He should know. The institute has spent as much as $1.3 billion on a state of the art research fab that has been working with EUV systems for years. It currently houses one of about eight of the latest systems installed worldwide.

Nearly all the top chip makers partner with Imec on pre-competitive research on next-generation nodes. This year Toshiba and Sandisk, two of the few holdouts, joined the program.

In a talk here, the head of ASML, the Dutch company developing EUV, gave a few new proof points of progress. One customer achieved for one week an 82% up time for one system, the NXE 3300B. ASML has a program targeting by the end of the year up time of 86% for the volatile light source.

The system is as critical as it is complex and troubled. Trillions of dollars are at stake in continuing the process of scaling to ever smaller chips, said Peter Wennik, chief executive of ASML in a talk here. "It’s a machine with a lot of industrial engineering problems — a whole slew of problems we will resolve one by one," he said.

Indeed every time ASML ratchets up the power on the light source which is critical to the throughput of the machine, some problem emerges in another module that has to be upgraded or redesigned to keep the machine running. "It’s a process of continuous engineering,” said Kurt Ronse, who heads the lithography program at Imec.

ASML is supplying EUV customers a prototype pellicle but may need to redesign it to support stronger light sources on the road map.

Today IBM, Imec, Intel, Samsung and TSMC are using at least one of the latest EUV systems. So far most but not all the systems have been upgraded to the 80W light sources. Most of the companies share at least some information on the systems’ performance in public forums with the exception of Samsung that has been mum so far.

The next big milestone comes at an EUV conference in October in Maastricht, the Netherlands. IBM, Intel and TSMC have all been invited to speak there.

"We have a lot of non-believers in EUV, but from a technical view it seems we will get there," said Wennik of ASML.

Indeed, observers think the tide may be turning. "We’ve all been skeptical on EUV, but it seems to be coming together now," said Malcolm Penn, principal of Future Horizons, a market watcher focused on semiconductors.

"There is a strong roadmap on throughput and that gives me confidence EUV will be ready for N7," said An Steegen, who heads Imec’s process technology research.

Nevertheless use of the expensive EUV machines will be limited to perhaps three critical layers in a chip. In such layers in a 7nm process, an EUV system can do in a single pass what would take three to five passes with today’s immersion steppers.

Without EUV the number of immersion litho steps will mushroom at 7nm.

Steegen believes a direct self-assembly technique, still in the lab, will first be used on the 7nm node. DSA could help reduce the amount of multi-patterning required.

If EUV systems are still not ready for production use in 18 months, chip makers will have to start work on 7nm without them. In that event 7nm will probably become a half node, not a full shrink, said Steegen. Restrictions on chip designers – that already have been significantly narrowed since the introduction of double patterning at 20nm – will get even tighter, she added.

"You relax your pitches and simplify your designs to become more lithography friendly…[and some lines] could require five exposures," she said.

In short, chips would get significantly more expensive to make than ever before. Probably only the largest FPGAs and processors would make use of the process. Profit margins would shrink, belts would get tightened and a lot of people would have a bad day.

In addition to the huge challenges in the lithography for making things, there also is a healthy debate on just what to make at 7nm. Steegen believes today’s 3-D transistors – FinFETs – will give way to a new style of gate-all-around nanowires.

New high mobility materials such as germanium may be needed as well. One analyst speculated last year Intel will make quantum well FETs starting at 10nm using germanium and indium gallium arsenide. Given the number of new elements – EUV, new transistor structures and new materials — the 7nm node could be one of the toughest in the history of the semiconductor industry.

ASML delivered its latest progress report on EUV at the event.

ASML will ship in time for the 7nm node an immersion system that can process more than 3275 wafers/hour.

Despite one recent upbeat forecast, the 10nm node may not deliver lower cost per gate, according to Imec’s Steegen. The node will be the first to require triple patterning on at least one and as many as six mask layers, adding a big tax to the final bill.

Most chip makers say costs per transistor rose at the leading edge 20 and 14/16nm nodes used today. Intel Corp. is an exception, claiming its costs continued to decline at 14nm. Market watcher Handel Jones recently predicted in general the 10nm node will be slightly more cost effective than the prior generations.

Steegen expressed skepticism about that prediction. "I know costs go up at 10nm, and I also know there are tricks to bring it down, but whether the net costs are less, stay at the status quo or go up could vary on a fab-to-fab basis," she said in an interview.

The extra masks costs for triple patterning are "substantial" compared to today’s processes that use double patterning, two passes through a lithography stepper for critical layers. A smart combination of process and design tricks could help mitigate those costs, but it’s unclear by how much.

Metal track scaling could provide more area, lowering per-transistor costs. In addition, some pitches could be relaxed, she said.

Wennick announced ASML will ship before the end of the year an upgraded immersion stepper capable of producing 275 wafers/hour, well above today’s 200 w/h level. Analyst Penn called that a very positive and surprising advance that could help mitigate 10nm costs.

It’s also possible EUV could arrive in time to be retrofitted into a sort of second-generation 10nm process. If so, it could handle one or more of the triple-patterning layers, although the machines would slow overall throughput. In addition, the systems are so expensive whether they actually lowered 10nm costs would depend on some creative accounting on their depreciation cycles.

"The decisions for 10nm have been taken to a large extent, but that doesn’t mean EUV won’t be retrofitted for it," said Van den Hove of Imec in a press conference. "I know several companies are very eager to use EUV at the 10nm node," he said.

The good news is most chip makers at 10nm are expected to make a second generation of FinFETs, a transistor type in which they have experience. Fins will get taller and thinner, as Intel has shown with its second generation FinFET process at 14nm.

More importantly, "N10 as far as we have analyzed provides a full node scaling," said Steegen.

Imec thinks a metal-tracking technique could reduce silicon area significantly (above), but it has performance drawbacks noted below.

Imec sees several ways to stack logic transistors, partly inspired by 3-D NAND.

As is usual with semiconductors, it’s almost impossible to predict what will happen in three generations, what people today call the 5nm node. Two things are clear: some new types of logic stacking may be required and researchers remain stubbornly optimistic.

EUV will not be available without major re-tooling. Something ASML said it has started work on now with Zeiss. At the event, Imec showed some early results of work on prototype 5nm devices. They required use of both quad-patterning immersion and EUV working together.

Steegen suggested horizontal nanowires might give way to new vertical transistor structures in the future. Logic needs something like the 3-D NAND breakthrough Samsung pioneered, she said.

The Imec research director showed a rough roadmap of various ways nanowires could be stacked to create ultra-dense chip designs. She also showed advances in thin through-silicon vias for linking chips stacked on top of each other.

In addition, she suggested today’s 2.5-D chips from AMD, Micron, SK Hynix and Xilinx could move beyond their current silicon interposers to use of silicon photonics.

The question is "how to smartly use the third dimension [so] we can reset the road maps like NAND," Steegen said. When the industry gets to "5nm or maybe 3nm, [we will find] a different stacking architecture and from there we will reset the clock and start counting nodes in a new way," she said.

"As long as the demand is there we will keep reinventing Moore’s Law, [the resulting structures] will not look anything like the conventional transistors we had 20 years ago, but there is a scaling path," she said.