Japanese researchers scale IGBT features for energy savings

Japanese researchers scale IGBT features for energy savings

Technology News |
By Graham Prophet

While progress in energy efficiencies has been reported with alternative materials such as SiC and GaN, energy-savings in standard inexpensive and widely used silicon devices are still keenly sought, the team observes. K Tsutsui at Tokyo Institute of Technology and colleagues in Japan studied silicon insulated gate bipolar transistors (IGBTs). While the efficiency of IGBTs is good, reducing the on-resistance, or the collector to emitter saturation voltage (Vce(sat)), could help increase the energy efficiency of these devices further.


Previous investigations have highlighted that increases in the “injection enhancement (IE) effect”, which give rise to more charge carriers, leads to a reduction in Vce(sat). Although this has been achieved by reducing the mesa width in the device structure, the mesa resistance was thereby increased as well. Reducing the mesa height could help counter the increased resistance but is prone to impeding the (IE) effect. Instead the researchers reduced the mesa width, gate length, and the oxide thickness in the MOSFET to increase the IE effect and so reduce Vce(sat) from 1.70 to 1.26V. With these alterations the researchers also used a reduced gate voltage, which has advantages for CMOS integration.


They conclude, “It was experimentally confirmed for the first time that significant Vce(sat) reduction can be achieved by scaling the IGBT both in the lateral and vertical dimensions with a decrease in the gate voltage.”


The researchers reduced the mesa width, gate length, and the oxide thickness in the MOSFET by a factor of 1/k, and compared devices with values of 1 and 3 for k. Because the fabrication of narrow mesas can cause problems they also reduced the trench depth by 1/k. Although this has a slightly negative effect on the IE effect, it has considerable benefits for fabrication ease and cost and the dependence of (Vce(sat)) on the trench depth was deemed to be small. The gate voltage was also decreased by a factor of 1/k, while the cell pitch was maintained at 16 μm. In the illustration, of the trench gate IGBT schematic, identified are; mesa width (S), gate length (Lg), and the oxide thickness in the MOSFET (tox), cell pitch (W), and the trench depth (DT).


K. Kakushima1, T. Hoshii1, K. Tsutsui1, et al, “Experimental verification of a 3D scaling principle for low Vce(sat) IGBT”, Technical Digest of IEDM2016, Session 10.6, (2016),


(the complete list of Authors are, variously, with Tokyo Inst. of Technology, Yokohama; Nat. Inst. Advanced Industrial Science and Technology, Tsukuba; Mitusbishi Electric; Toshiba Corp; University of Tokyo; Meiji University, Kawasaki; and Kyushu Inst. of Technology, Kitakyushu, Japan.)



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