JEDEC preps finalization of HBM4 standard
The JEDEC Solid State Technology Association has announced it is nearing completion of the next version of its High Bandwidth Memory (HBM) DRAM standard: HBM4.
The HBM4 standard has been designed to be an evolution from HBM3 with a double channel per stack and a larger physical footprint. To promote introduction JEDEC has contrived HBM4 so that a single controller can operate with both HBM3 and HBM4.
Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 Gbit and 32 Gbit DRAM layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has initial agreement on speeds bins up to 6.4 Gbps with discussion ongoing for higher frequencies.
In October 2023, SangJoon Hwang the head of the DRAM team at Samsung Electronics said that he expected HBM4 products to be introduced by 2025 with technologies optimized for high thermal performance, such as non-conductive film assembly and hybrid copper bonding.
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