JESD204B is a high-speed serial interface standard that greatly simplifies circuit board design when interoperating FPGAs with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Altera has validated device interoperability with leading data converter suppliers, including Analog Devices and Texas Instruments (TI), and is actively working to expand its offering by validating interoperability with many other data converter companies.
The company is providing intellectual property (IP) cores, reference designs, development boards and interoperability reports for the industry’s latest data converters. The collection of JESD204B resources is available through an online resource center that enables users to jumpstart the development of JESD204B-based serial interfaces, while giving designers the flexibility to select the FPGAs and data converters that best meet their systems’ power and performance requirements.
Altera offers JESD204B solutions that support its latest 28 nm products, including high-performance Stratix V FPGAs; mid-range Arria V FPGAs and SoCs; and low-power, low-cost Cyclone V FPGAs and SoCs.
“Our close collaboration with industry-leading partners enables us to deliver the most comprehensive JESD204B offering in the FPGA industry,” said Alex Grbic, director of software and IP product marketing at Altera. “Providing validated device interoperability reports, proven IP, and multiple reference designs and development kits allow customers to quickly evaluate and integrate a JESD204B-based serial interface into their designs.”
Altera provides JESD204B IP that includes the physical layer, data link layer and transport layer implementations from a single source. The IP conforms to the latest JESD204B standard for operation up to 12.5 Gbps. Demonstration videos and full interoperability reports are available at www.altera.com/jesd204b.
Altera features a JESD204B resource center on its web site that simplifies the evaluation and selection of data converters from industry-leading vendors. Through this resource center, customers can find out more information about Altera’s JESD204B solutions, download and evaluate JESD204B IP, view device interoperability reports and characterization reports, and download reference designs. Demonstration videos are also available for viewing within the Altera JESD204B resource center that detail the set up and hardware used in several systems. Altera offers free technical training modules that can help designers familiarize themselves with Altera high-speed serial IOs and related software tools.
Altera’s JESD204B solutions, including fully tested and proven IP, reference designs and development kits, are available today. The JESD204B IP is available for download and free evaluation.