Jitter attenuator optimized for JESD204B interface
The 3.2GHz HMC7044 delivers 50-fs jitter performance, which improves the signal-to-noise ratio and dynamic range of high-speed data converters, and the device provides 14 low-noise and configurable outputs.
The HMC7044 also offers a range of clock management and distribution features that make it possible for designers of communications basestations to base an entire clock design on a single device.
HMC7044 clock jitter attenuator generates source-synchronous and adjustable sample and frame alignment (SYSREF) clocks in a data converter system. The device features two phase-locked loops (PLLs) and overlapping, on-chip, voltage-controlled oscillators (VCOs). The first PLL locks a low-noise, local voltage-controlled clock oscillator (VCXO) to a relative noisy reference, while the second PLL multiplies the VCXO signal up to the VCO frequency with little added noise.
For cellular infrastructure JESD204B clock generation, wireless infrastructure, data converter clocking, microwave baseband cards and other high-speed communications applications, the architecture of the HMC7044 offers low phase noise and integrated jitter.
HMC7044 clock jitter attenuator key features
• JEDEC JESD204B support
• Ultra-low RMS jitter: 50 fs (12 KHz to 20 MHz, typical)
• Noise floor: -162 dBc/Hz at 245.76 MHz
• Low phase noise: < -142 dBc/Hz at 800 kHz to 983.04 MHz output frequency
• Up to 14 device differential device clocks from PLL2
• External VCO input supports up to 5 GHz
• On-board regulators for excellent PSRR
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