JTAG standards and mixed-signal test instruments embodied in one IC
Various operation modes of the IC enable a wide range of applications of the chip as bus transceiver, pin driver and system monitor. For flexible signal adaptation, different interface types with programmable transceiver parameters have been integrated into the chip.
“The third generation of JTAG transceivers is our approach to solving the problem of ultra-low voltage applications. Additionally, with the CION LX we have combined various analogue and digital test instruments with one extensive Boundary Scan architecture in a unique way”, says Thomas Wenzel, Managing Director of Goepel electronic’s Boundary Scan Division. “At the same time, our new IC provides an excellent starting position for the development of more powerful I/O modules.”
The CION LX was developed in 0.35-µm mixed-signal CMOS technology and provides four independent I/O ports. Each port can be individually operated in a voltage range from 0.9V to 3.6V. The integrated Boundary Scan architecture supports the IEEE 1149.1, IEEE 1149.6 and IEEE 1149.8.1 standards, at a maximum TCK frequency of 100 MHz. In addition to the single-ended pins, the CION LX provides differential signals as well as interfaces with increased driver ability. Four operation modes enable the IC to operate, variously, as a purely serially controlled JTAG transceiver, parallel I/O buffer, latched bus transceiver, or pin driver.
Instruments such as digitiser, arbitrary waveform generator, event counter, frequency meter and toggle detectors are integrated into the CION LX. These instruments can be accessed – depending on operation mode – either serially via the JTAG Test Access Port (TAP) or a parallel control bus. The instruments can be activated simultaneously to Boundary Scan operations and per test channel. For each channel, pull-up and pull-down resistors can be additionally connected. It is also possible to program the drivers‘ slew rates.
CION LX is currently available as a sample. First series deliveries are planned for Q3 in 2013. A QFN housing with 116 pins will be used. There will also be a version with 64 pins compatible with the footprint of a predecessor IC.
Goepel electronic, www.goepel.com
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