KAIST researchers make paper flash memory

KAIST researchers make paper flash memory
Technology News |
In a paper titled "Organic flash memory on various flexible substrates for foldable and disposable electronics" published in Nature Communications, researchers from the Korea Advanced Institute of Science and Technology (KAIST) share their very promising results for a novel type of cheap and ultra-thin flexible flash memory for wearable or disposable applications.
By eeNews Europe


The organic memory architecture, based on C60-based organic Thin Film Transistors (TFTs) relies on thin polymer dielectrics sandwiching a floating gate electrode under the transistor channel (instead of a simple gate insulator).

The flexible flash memory structure (top) and
a false-color cross-sectional TEM image of the
fabricated device (bottom). Courtesy of KAIST.

Key to achieving the near-ideal dielectric characteristics required for the Tunnelling Dielectric Layer (TDL) between the channel and the Floating Gate (FG), and for the Blocking Dielectric Layer (BDL) between the floating gate and the Control Gate (CG) was the initiated chemical vapour deposition (iCVD) process used to build up the memory stack, explain the authors.

This solvent-free vapour-phase growth technique for polymers can be applied at low temperature on many different substrates including PET and paper as the researchers demonstrated with their flexible flash memory. The main challenge solved thanks to the use of iCVD was to design dielectric layers thin enough to enable low-voltage programming/erasing while ensuring leak-free insulating properties.

In their design the researchers carefully considered both applied and built-in electric fields across the dielectric layers for each operating condition, choosing poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) and poly(ethylene glycol dimethacrylate) (pEGDMA) for the TDL and BDL films respectively. Because the iCVD process yields a conformal polymer growth, it minimizes the risk of forming accidental electrical shorts, it also yields near-ideal dielectric layers with low trap densities, noted the researchers in their paper.

Electric field distribution (shown as arrows) inside the
flash memory under programming (left) and erasing
operations. Courtesy of KAIST.

Designed with a 40 nm-thick BDL (pEGDMA) and a 16nm-thick TDL (pV3D3) on a 250μm-thick PET substrate, the flexible memory devices operated with programming/erasing voltages (Vprg and Vers) as low as ±10V comparable to those of conventional Si-based flash memory devices. What’s more the devices exhibited reliable programming and erasing behaviours for thousands of cycles, with a retention time estimated to around 10 years (an extrapolated value of the electrical aspects only, added encapsulation would be required for actual long-term testing). Programming and erasing times were as low as 10ms.

When tested under flexural tensile strain (flexed around a piano wire), the devices showed consistent programming/erasing behaviours, reports the paper, maintaining their memory characteristics even after over 10,000 bending cycles. Both dielectric layers maintained their insulating property at a tensile strain of up to 4% (that compares favourably to inorganic dielectric layers which typically lose their insulating property with strain of ~1%.

Under flexural strain, the flexible flash memory being
rolled up around a piano wire. Courtesy of KAIST.

The researchers also fabricated devices on 6μm-thick Mylar films using a 33nm-thing BDL and a 17nm-thin TDL, which made the flash memory easily bendable over a needle. Here again, the ultra-thin flash memory maintained its programming and erasing capabilities in the folded state, even after over 1200-time folding cycles (at a bending radius of 300μm).

To push their experiments further, the KAIST researchers leveraged the iCVD process’ conformal coating capability and low-temperature operation to build an organic flexible memory on rough uncoated paper (with surface bumps at both the micro- and nano-scale).

Without any planarization (or conformal coating), they were able by building a thicker pEGDMA base layer (111nm) to create a workable paper memory, albeit requiring higher programming and erasing voltages of ±25V. Those voltages were reduced to ±15V by first applying a 1.5μm-thick poly(divinylbenzene) planarization layer to smoothen-out the nano-scale bumps of the paper before building up the memory stack.

The researchers hope their novel fabrication approach will open the way for cheap ultra-thin and disposable flash memory devices for use in epidermal or imperceptible electronics, emphasizing that their results demonstrate the potential of the iCVD process for creating flash memories on almost any kinds of flexible substrates.

KAIST – www.kaist.edu

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