Lattice moves to 16nm CMOS for its FPGAs

Lattice moves to 16nm CMOS for its FPGAs

Technology News |
By Nick Flaherty

Lattice Semiconductor has launched a new platform for its field programmable gate arrays, moving to 16nm CMOS from its previous 28nm FD-SOI (fully depleted silicon on insulator)

The move allows Lattice to take on AMD/Xilinx and Intel directly with higher density FPGAs with up to 500,000 logic elements. Coming to a 16nm FINFET process many years later than its competitors allows more of the interface blocks to be diffused into the CMOS fabric to cut the power consumption.

However the move to the new platform maintains the software stacks from the previous Nexus platform, giving existing customers immediate access to higher density devices.  

The Avant family of FPGAs starts with the Avant-E and will be a platform with different variants. This is likely to include different diffused interface blocks and smaller densities at 200,000 and 300,000 logic elements.

The Avant-E has the highest density of the family with configurable SERDES up to 25 Gbit/s, hardened support for PCIe Gen 4, high performance I/O, and high speed memory interface support including LPDDR4 and DDR5.

The PHY (PMA+PCS) layer is hardened and supports several protocols including PCIe Gen 1/2/3/4, 1G/10G/25G Ethernet, JESD 204B/C, CPRI, eCPRI,  Display Port, SLVS-EC, and several others. The memory PHY portion is hardened and uses a DFI DDR PHY Interface but the protocol controller is soft.

“Just as we’ve done with our Nexus platform, we have a strong and steady roadmap of future product introductions based on the Avant platform. To make designing with Lattice Avant FPGAs as easy as possible, Avant will be fully supported by our robust software tools and application-specific solution stacks,” said Steve Douglass, Senior Vice President of R&D at Lattice Semiconductor.

The chips and boards for Avant-E have been with early customers for the last three months, and Lattice has run a number of demonstrations using the software stacks.

The AI demo implements 22 layers of a modified MobileNet v1 machine learning framework. This takes in video with a resolution of 1080p60 that is scaled down to 480×288 for neural network processing by pre-processing block of FPGA. The result is overlaid on top of 1080p60 video for display.

A power consumption demo uses a pattern of around 250K logic blocks designed to primarily exercise the FPGA fabric with an activity factor of 10% to 15%. This shows that the 500K Avant-E can operate with a 2W power consumption at 250MHz, compared to 5W for Intel’s Aria FPGA.

“That will allow us to deliver packages that are smaller,” said Jay Aggarwal, director of silicon product marketing at Lattice, pointing to the 13 x 15 mm package with a 0.5mm pitch for space-constrained designs, although there are larger pitches for easier manufacturing.  

Lattice is planning production in the first half of 2023, says Aggarwal.

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