Lattice reference design enables ISP to interface with Aptina HiSPi CMOS sensors
Image Signal Processor (ISP) with a traditional CMOS parallel bus to interface with an Aptina HiSPi CMOS sensor.
The HiSPi bridge solution is ideal for security cameras, automotive applications, high end consumer cameras and other camera applications where the use of higher resolution and higher frame rate CMOS sensors is desirable.
“This is the second successful project we have worked on with Lattice, after the well-received HDR-60 video camera development kit using an Aptina MT9M024 sensor. We are pleased to be working with Lattice again. This new LatticeXP2 FPGA-based HiSPi bridge chip is very useful to customers who want to adopt Aptina’s high resolution, high performance image sensors,” said Cliff Cheng, Aptina Senior Segment/Business Development Manager.
The free HiSPi bridge reference design supports all modes of the Aptina HiSPi specification and is available at www.latticesemi.com/sensorbridge. Users can download any of the common HiSPi interface designs, or use the HiSPi configuration tool to generate a specific HiSPi bridge for their needs. The LatticeXP2 FPGA supports from one to four HiSPi data lanes up to 700Mpbs. HiSPi formats of Packetized-SP, Streaming-SP, Streaming-S or ActiveStart-SP8 are supported. The HiSPi bridge is also designed to provide support for sensors in linear or HDR mode. The parallel bus interface to the ISP is configurable from 10 to16 bits and the voltage level can be set from 1.8 to 3.3 V.
Visit Aptina at www.aptina.com
Visit Lattice Semiconductor at www.latticesemi.com
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