Lattice updates security FPGA range with 384bit security
Lattice Semiconductor has updated its security FPGA range with a 384bit security enclave and RSIC-V processor on a low power 28nm FDSOI process.
The Mach-NX family enables a hardware root-of-trust validation and security, and is initially aimed at protecting data centre servers cards. The device includes a hardened RISC-V core and a 384bit encryption engine, or security enclave, alongside 11,000 logic cells.
This builds on the MachXO3D devices launched last year that are currently shipping on 80 percent of server cards and is the third FPGA family developed on the 28nm SOI Nexus FPGA platform this year. It includes a physically unclonable function (PUF) to generate a unique random number based on the structure of the individual device.
“We have hardened many of the blocks with the RISC-V core dedicated to configuring the features of the PFR and the security of the secure enclave,” said Peiju Chiang,product marketing manager at Lattice. “Our customers are the experts in their board management needs, we make it easier to integrate a security block using RISC-V and Lattice Propel tool.”
The chip supports two configuration images stored in embedded flash memory that are signed for security to allow secure over the air (OTA) updates.
The RISC-V core is a standard implementation, and the circuit design includes techniques to avoid side channel attacks such as monitoring the current or thermal activity to determine encryption keys. The logic allows other custom encryption to be added to the chip.
“You can build another RISC-V in the user logic if you want,” he said.
The Mach-NX FPGAs support the Lattice Sentry software stack, a combination of customizable embedded software, reference designs, IP, and development tools to accelerate the implementation of secure systems compliant with NIST Platform Firmware Resiliency (PFR) Guidelines (NIST SP-800-193).
Lattice is also pushing its place as an independent supplier in the data centre if the proposed AMD-Xilinx deal goes through. This is likely to see bundling of Xilinx devices with AMD processors for server cards.
“With all the consolidation in the FPGA space we remain independent,” he said. “We are giving the customers choice and not biased to one processor over another.”
The first version of the chip will be in a 19 x 19mm 484 BGA, with alpha samples currently shipping and production the first half of 2021. A 256 pin version will be available in the second half of 2021 for more space-constrained designs.
“The primary market is servers, those are using Eagle Stream platform,” said Chaing. “The 256 pin version is still targeting that sector as well, but as we expand the idea we can generate other packages to meet the needs of different segments. Its for size reasons and for modular approaches where a smaller device is becoming more interesting.”
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