Lauterbach’s debug tool now supports the EMSA5-FS functional safety processor core developed using the open RISC-V instruction set architecture.
EMSA5-FS was developed by Fraunhofer Institute for Photonic Microsystems (IPMS) as the first fault-tolerant embedded RISC-V core with functional safety certified as ASIL-D ready.
Lauterbach’s TRACE32 toolset now supports the EMSA5-FS and offers developers extensive debug functions. The core can be made available for any FPGA platform and can be integrated into customer-specific ASICs for a wide range of foundry technologies. Fraunhofer IPMS also provides services to extend the IP core with customer-specific modules.
Related RISC-V articles
- ARM battles RISC-V at Renesas
- Tackling the challenges of RISC-V
- Fraunhofer extends RISC-V core for edge AI
- Fraunhofer zooms RISC-V into functional safety
“The inclusion of the EMSA5-FS processor core in Lauterbach’s TRACE32 toolset represents an important milestone for us,” said Marcus Pietzsch, head of the IP Cores and ASIC Design group at Fraunhofer IPMS. “By working closely with Lauterbach, we can now offer developers additional functionality around debugging software on the RISC-V IP. Developers working with our processor core will thus benefit from the advantages of working with a first-class tool.”
The TRACE32 toolset provides multicore debugging on individual hardware threads of RISC-V cores and enables debugging directly from the reset vector, which is needed to test startup codes and other key functions. Lauterbach also provides high-level and assembly debugging for a variety of standard ISA extensions, such as Compressed Instructions and Floating Points. In addition, the JTAG debug transport module (DTM) is fully supported.
The EMSA5-FS is suitable for implementing microcontrollers in automotive, aerospace, medical and other safety-critical devices and systems.
Other RISC-V tool articles
- Ashling tools for RISC-V space processor
- Intel taps Ashling for RISC-V development tools
- Ashling to supply toolchain for MIPS RISC-V cores
- Segger, HPMicro team on free RISC-V tools
- Segger licenses ARM and RISC-V compiler and linker
Other articles on eeNews Europe
- $400m RISC-V design centre for Barcelona
- Renesas buys edge AI tool developer
- AI optimisation moves into system design tools
- Cognifiber benchmarks its photonic AI performance
- Apple boosts transistor count in 5nm M2 chip
- €140m 3D chip research centre opens in Dresden