Layout-dependent effects in analog design
Analog designers have always had to worry about physical layout to get good matching of devices. Variations in doping levels across the chip, usually assumed to be in a gradient in one or two dimensions, could be handled by clever layout such as common centroid devices. The same is true for temperature variations created by on-chip power devices: With currents of 10 A or more on power conversion/regulation devices, thermal gradients become a real issue.
As process geometries reduced, a new type of variability was introduced – collectively known as “layout-dependent effects” or LDE for short.
One example of an LDE is the proximity of devices to the well edges. The distance of devices to a well edge has an effect on the Vt (threshold voltage) of the device. The cause is implant ions scattering off the resist sidewall used to define the well, thus increasing Vt by several to tens of millivolts. (See “Layout-Dependent Proximity Effects in Deep Nanoscale CMOS,” John V Faricelli, IEEE CICC 2010.)
How Vt varies with spacing from well edge.
The change in Vt can give rise, not only to mismatch effects, but also to significant performance changes. Other effects can be due to unintentional stresses in the silicon, caused, for example, by shallow trench isolation between devices. This stress affects carrier mobility in the devices and, hence, current. This is known as a “length of diffusion” or LOD effect, where the characteristics of a device vary according to the distance of its gate from the diffusion edge.
To design with LDE effects, various layout techniques can be used:
- Use similar diffusion size, shape and orientation;
- Use a larger separation for devices to the well edge;
- Add dummy devices and/or dummy poly to make fingered devices more equal.
However, accurate simulation of the design requires early layout and, with it, parasitic extraction, to be able to model the LDE effects during simulation. All this breaks existing custom design flows, which traditionally have a circuit designer hand off a preliminary schematic, simulated possibly with estimated parasitics, to the layout engineer, who then creates an initial layout for extraction of the real parasitic values. This then gets handed back to the circuit design to optimize device parameters to meet the performance goals, and often takes several layout/optimization iterations.
An automated analog layout tool, such as Pulsic’s Animate, can identify constraints intended by the designer and rapidly generate multiple real layouts in minutes. These layouts can then be extracted and simulated, allowing designers to take into account LDE effects much more quickly without sacrificing performance.
Keith Sabine, product manager for analog solutions at Pulsic Ltd. (Bristol, England), has 35 years of experience in the semiconductor and EDA industries, starting out as a bipolar designer at Fairchild Semiconductor before moving into CMOS process development and characterization at Plessey Semiconductors. His EDA career has included time at Cadence, Simplex, Apache, and now Pulsic.
This article first appeared on EE Times’ Planet Analog website.
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