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Leakage-free germanium nanowire transistor beats silicon

Technology News |
By Julien Happich


Using a germanium nanowire as a non-doped channel, a team of researchers from the Nanoelectronic Materials Laboratory (NaMLab GmbH) and the Cluster of Excellence Center for Advancing Electronics Dresden (cfaed) at the Dresden University of Technology has devised a dual-gate transistor that not only efficiently suppress leakage but can also be programmed between electron-(n) and hole-(p) conduction.

Top-view SEM image of a multi-gated germanium
nanowire transistor. The scale bar is 400nm

In a paper titled “Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions” published in the journal ACS Nano, the researchers report a device layout with two independent gates used to induce an additional energy barrier to the channel that blocks the undesired carrier type.

The researchers show that the polarity of the same doping-free device can be dynamically switched between p- and n-type, outperforming previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents.

Schematic device layout showing
the program gate and the control gate.

Although the concept is proven experimentally (and the results corroborated using finite-element analysis) with a germanium nanowire Schottky barrier field effect transistor (FET), the researchers reckon that the same basic approach of having multiple gates is transferable to other types of FETs, , including tunnel FETs, spin-FETs or junctionless transistors.


An interesting feature beyond the suppression of leakage in the off-state, is that the device can be dynamically programmed to resemble both p-type and n-type functionality within a single device without using any kind of physical doping, and this “programmability” feature could be used to multiply the number of functions in a given circuit.

Indeed, the researchers also explored such options in another paper, “Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits” to be presented at this year´s DATE conference (Lausanne, March 27-31). In that paper, several combinational circuits that use p- to n- reconfiguration are showed, including a 2 input Multiplexor (MUX) and an 8-bit Conditional Carry Adder (CCA) amongst others.

Cross-sectional TEM image below one of the
two top-gates.

“Although there is an overhead in gates and a larger transistor cell is required, thanks to the p- n- re-configurability those circuits require a lower chip area. The 2-MUX cell occupies only 65 % of the area compared to CMOS. The 8-bit CCA uses 84% of the area” revealed Dr. Walter Weber, Senior Scientist at NaMLab GmbH, in an email exchange.
“That analysis was made with silicon based reconfigurable transistors. In those reconfigurable circuits, the use of Germanium instead of Si can reduce the supply voltages to more than the half of the value. The dynamic power consumption is then reduced to a fourth of the value” Weber added.

Although the proof-of-concept was realized with fairly large device structures, further analysis and finite-element drift-diffusion simulations revealed that both leakage current suppression and polarity control can also be achieved at highly scaled geometries.

Access the publication at https://pubs.acs.org/doi/abs/10.1021/acsnano.6b07531

Visit the Nanoelectronic Materials Laboratory gGmbH (NaMLab) at www.namlab.com

Visit the Center for Advancing Electronics Dresden (cfaed) at www.cfaed.tu-dresden.de

 

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