Leonardo uses Mentor tool to accelerate radar FPGA verification
Leonardo has been using Mentor’s Questa SystemVerilog verification tool as part of a Universal Verification Methodology (UVM) framework with Questa Verification IP (QVIP) for the verification and validation (V&V) of avionics radar interfaces. Incorporating the UVM framework, QVIP and Verification Run Manager into a Jenkins software-based environment has provided more value within the toolkit as it allows automated reverification of designs after modification.
Electronically scanned array radar systems contain a multitude of central processing units (CPUs) and FPGAs, spread across several subsystems, with the FPGAs implementing control, digital signal processing (DSP) and communication functions. “Designing a complex system like this is a daunting task, especially when you take into account the tight schedule demanded by today’s fast-paced marketplace,” said Iain Wildgoose, vice president of Engineering, Radar and Advanced Targeting for Leonardo’s Airborne and Space Systems Division. “The reuse and scalability that the UVM framework and QVIP delivered, combined with the support to the adoption process provided by Mentor consultants and application engineers, were key enablers to successful design and integration.”
Mentor QVIP provides a library of verification IP for more than 40 standard protocols and 1,700 memory devices. QVIP includes checkers and coverage, plus a comprehensive set of stimulus sequences for the protocols. Adoption of QVIP IP for the standard interfaces enabled Leonardo to focus on the unique specifics of the company’s design. QVIP and the UVM framework — a set of base classes layered on top of UVM — have enabled Leonardo to increase code coverage significantly in a short period of time.
Using the UVM framework reduces the time needed to create test benches as well as the interpretation of test bench results, through abstraction of this task to a higher level. Leonardo was able to deploy Questa across projects to accelerate test bench development and efficient coverage closure. After these initial successes, Leonardo is now deploying the UVM framework to other projects across the company.
“Increasingly complex FPGA designs demand reusable and scalable verification solutions that accelerate development and increase overall quality,” said Ravi Subramanian, vice president and general manager, IC Verification Solutions Division at Mentor, now part of Siemens. “The Questa solution, coupled with the UVM framework and QVIP, reduces testbench and VIP development time by automatically generating project test benches. Our industry-leading application engineers, consultants, and online resources enable easy adoption of these techniques that will pay dividends for many projects to come.”
Related stories:
- DESIGNING PRODUCTS WITH HIGH-SPEED CONSTRAINTS
- AN INTELLIGENT DFM APPROACH TO PCB MANUFACTURING
- DESIGN REUSE FOR PCBS
- THE BENEFITS OF MODEL BASED ENGINEERING IN PRODUCT DEVELOPMENT
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
