Leti pushes 300mm wafer-to-wafer hybrid bonding to 1µm-pitch for 3D ICs
Wafer-to-wafer bonding is an essential process step to enable 3D stacked integrated circuits and the copper/oxide hybrid bonding process is a key enabler for such applications. It was demonstrated in Leti’s cleanrooms using EVG’s fully automated GEMINI FB XT fusion wafer bonding system, at a pitch of 1µm with copper pads as small as 500nm.
This result was obtained in the framework of the program IRT Nanoelec headed by Leti. EVG joined the institute’s 3D Integration Consortium in February 2016. In order to shrink IC dies, tight alignment and overlay accuracy between the wafers is required, not only to minimize the interconnect area at the bond interface but also to ensure good electrical contact between the interconnected device on the bonded wafers.
In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in the GEMINI FB XT automated production fusion bonding system, which incorporates EVG’s proprietary SmartView NT face-to-face aligner and an alignment verification module to enable in-situ post-bond IR alignment measurement. The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centered below 15nm. Post-bake acoustic microscopy scans of the full 300mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.
“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking.”
This demonstration is summarized in a paper co-authored by Leti, titled “1 µm Pitch Direct Hybrid Bonding with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.
“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “As a leader in 3D integration research and development, Leti has been at the forefront in moving this critical technology toward industry adoption and commercialization. EVG shares that vision, and we are pleased to have played a role in supporting Leti’s latest achievement in 3D integration.”
The GEMINI FB XT can accommodate up to six pre- and post-processing modules for surface preparation, conditioning and metrology steps such as wafer cleaning, plasma activation alignment verification, de-bonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding.
Leti – www.leti-cea.com
EV Group – www.EVGroup.com
Nanoelec Research Technological Institute (IRT) – www.irtnanoelec.fr
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