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Leveraging decoupling capacitance of regular power grids

Leveraging decoupling capacitance of regular power grids

Technology News |
By eeNews Europe



With each passing year and each lower technology node, design speeds are increasing tremendously. High frequency designs take a toll on the power integrity of ICs and induce more noise and ringing into the power supply network because of the increased signal switching speeds. This leads to the need for increased decoupling capacitance to address the power supply noise.

The decoupling capacitance required in this case would be most beneficial, if present on the die itself. However, more on-die decap implementation would be an overhead and would increase silicon cost. Hence, there is a strong need to increase the effectiveness of the ‘used-up’ resources on the die to reduce the cost overhead, without impacting any of the existing design parameters. This paper discusses a method for increasing the effectiveness of the power grid mesh and providing additional on die decoupling capacitance at no extra cost.

Problem definition

A methodology to increase the inherent capacitance of the power grid without compromising any of the existing parameters of the chip which the power grid directly effects such as voltage drop (or the current carrying capability of the grid) and the routability (or the space left over by the grid for signal net routing) of the design is discussed. The increased capacitance between power and ground supply enabled by this technique acts as additional decoupling capacitance. This additional capacitance helps decrease dynamic voltage drop by acting as a distributed local current source to the sudden demands of current due to highly concentrated, high frequency local switching.

Figure 1 illustrates how decoupling capacitance helps in decreasing dynamic voltage drop. As can be seen, a charged capacitor acts as a local current source to the sudden demands of current by the device. Since all the current is not being drawn all the way from the pads, the voltage drop is less. When the sudden demands of current cease to exist, the capacitor is charged again. In this way, the decoupling capacitor helps reduce the ringing in the power grid by averaging out the noise peaks.

The chip level power grid for synthesizable designs is drawn in the form of a mesh of metal stripes with each alternating metal laid out at right angles to the preceding metal. The current implementation of the power grid structure (width and frequency of stripes) is based on two criteria: IR drop and design routability.

Since the intent is always to close the design using the least possible area, the power grid has to be optimized in terms of widths and stripe placement to provide a balanced trade-off between the voltage drop and the routability. A good amount of resources get used in the power grid design (on average 15 percent on-die metal is for routing). The methodology discussed herein is intended to be a “welcome by-product” off this already “used-up” power grid without impacting any of the existing parameters. A sample conventional power grid snapshot view is shown in Figure 2.

Looking at capacitance to drive relative placement
Our solution is to use the basic fundamentals of metal plate capacitance to drive the relative placement of power and ground stripes in a power grid. This informed relative placement increases the local capacitance between the power and ground lines, which acts as a local current source and provides decoupling between power and ground lines, hence improving the power integrity of the design and reducing the power supply noise.

Figure 3 is a 3-D snapshot of metal4 and metal6. Other metal layers have similar profiles. Two improvements to the power grid structure are provided for increased decoupling capacitance. The power and ground stripes in the same plane have been brought together and placed alongside at the minimum possible distance allowed by the design rule spacing’s. This increases the side-wall capacitance between power and ground to the maximum possible.

In the planes which have the same metal routing direction we have placed the power (vdd) and ground (vss) stripes in such a way that a vdd stripe in M4 is sandwiched between vss stripes in M2 and M4. Similarly a vss stripe in M4 is sandwiched between vdd stripes in M2 and M6. This increases the area capacitance between power and ground to the maximum possible. Figure 4 shows actual 3-D snapshots of metal4 and metal6 for a conventional design. Other metal layers have similar profiles. Figure 5 illustrates the physical implementation of the power grid mesh using such a methodology.

There is no decoupling ‘area capacitance’ effect in the conventional approach to the next level metal layer (eg. Metal6 to Metal4) and “side-wall’ capacitance is 60 times less in the conventional approach.

Experimental results
To prove this concept, a power grid was implemented following both the conventional and the proposed designs, using a C65 process on a 25mm² die. The power and ground mesh was then extracted for capacitance. As shown in Table 1, using the same resources, the decoupling capacitance was increased nearly three folds with the new methodology, without affecting the voltage drop and the routability found in the conventional design.

The resultant increase in power-ground capacitance decouples any noise induced between these nets due to high frequency circuitry. What’s more, the actual implementation of the proposed methodology is straight forward and does not require any change of tools.

About the author:
Chetan Verma is senior design engineering manager at Freescale Semiconductors India.
He can be reached at chetan@freescale.com
www.freescale.com    

Courtesy of eeNews Europe

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