Linearity testing for G.hn PLC line drivers, pt.1
Emerging in home wideband PLC networks are pushing the transmit frequencies through 50MHz today and possibly through 100MHz carriers into the future. The line driver must not only deliver the desired signal onto a difficult load, but must also not introduce a non-linear load during its shutdown for this TDMA system.
Since these systems act like a party line on the in home power lines, where a single transmitter is enabled while all other PLC ports show a disabled line driver in parallel with the receivers, those disabled ports must be able to receive the signal without introducing excessive nonlinearity into the broadband load. Test methodology and data on a 3rd generation wideband differential driver will be developed in 2 parts.
Part 1, below, describes the required characterization steps for a single port driver into a passive lab load. This will step through the source signal generation, driver configuration, and measurement methodology to rapidly assess the MTPR across a 2MHz to 50MHz Discrete Multi-Tone (DMT) modulation band. Part 2 will add a 2nd driver to the load network showing a measurement setup for introducing this active load while tapping off the transmit signal for MTPR degradation measurement.
Line driver test methodology and hardware for rapid lab characterization
Common to all DMT based wireline driver characterization requirements is the need to generate low distortion test signals and quickly analyze the resulting spectrum for MTPR (Multi-Tone Power Ratio) degradation from the input signal caused by the line driver. The G.hn requirements run in the -45dBc to -50dBc MTPR line driver linearity requirements. Since all Intersil DSL/PLC line drivers are intended to deliver moderate gains (15->25dB), the input signal swings are relatively modest and can be easily supplied by AWG equipment. Figure 1 shows a typical setup where several optional elements are included.
Click on image to enlarge.
Here, a Tektronix AWG5002B generates the correct time waveforms for the desired PSD (Power Spectral Density) mask where typically every 5th or 6th transmit tone is missing. It is the intermodulation of the carriers into these missing tones that defines the MTPR. This test is very similar to the NPR (Noise Power Ratio) test in uWave channels where instead of noise as a test signal, the actual PSD achieving the desired line power and crest factor are used with intentionally notched out tones. While the AWG5002B provides excellent MTPR an additional postamplifier was added to:
- Isolate the AWG from any DUT disturbances that might feed back into its output ports.
- Reduce the peak swing requirements for the AWG by the preamp gain possibly improving its delivered MTPR. This is particularly useful if the DUT is lower gain requiring higher input swings.
- The ISL55210 preamp board also included a 9th order passive filter to eliminate any higher frequency AWG artifacts. This becomes more important if the spectrum analyzer is replaced by a wideband ADC data capture card (as it will be here).
The actual line driver in figure 1 is a 3rd generation single port differential push pull device, the ISL15100 (ref. 1). The DUT block in fig. 1 is either another ISL15100 line driver in disabled condition or, in this initial characterization, the 100Ω line load emulation typical of PLC systems. The actual load impedance will be reduced from 100Ω by the turns ratio assumed for the implementation. From the DUT output, the differential signal is passively converted to single ended and scaled by a tunable attenuator to deliver it into either a spectrum analyzer or wideband data capture card. Figure 2 shows the hardware for the signal flow of figure 1.
Click on image to enlarge.
Here, the spectrum analyzer of fig. 1 is replaced by what an FFT based spectrum analyzer (far right) operated by PC based FFT analysis software (ref. 2). Using a standard spectrum analyzer to measure the DUT output power at each of the 1920 tone carriers for the 2Mhz to 50MHz PLC PSD took several hours running under LabView control, while this commercially available 100kHz to 100MHz board based spectrum analyzer reduced that to <1minute. Typical single tone -1dBFS tests for this 12bit, 500MSPS (ref.3) based design delivers better than -80dBc SFDR which is adequate for any of the DSL/PLC line driver test requirements.
The differential I/O preamp (at the left of figure 2) terminates the 2-50Ω AWG outputs into an AC coupled 100Ω differential load implemented as a 9th order passive filter followed by the ISL55210 (ref.4). These details can be seen in figure 3 (ref.5).
Click on image to enlarge.
The 4GHz Gain Bandwidth Product ISL55210 provides one of the lowest distortion gain stages from low frequencies to well above 100MHz. Typical HD3 and IM3 performance for a 2Vpp output are <-110dBc through 100Mhz providing an excellent external postamplifier option for any differential output AWG. The intended operating range for this postamplifier was 100kHz to 50MHz with excellent phase linearity and a rapid stop band rolloff.
The 9th order Butterworth was set to a 95Mhz cutoff to hold constant group delay through 50Mhz but provide significant attenuation at higher frequencies as shown in the measured response of figure 4. It is probably more common to put this higher order filter after the amplifier to remove any amplifier introduced distortion terms. However, since the ISL55210 provides >55dBm 3rd order intercept below 50MHz (using only 115mW) nothing that is not in the input spectrum will be added at the gained up output spectrum. This allows the interstage coupling to the PLC line driver to be set with resistors eliminating any issues the line driver input stage (or other device under test) might have with out-of-band source impedances for complex passive filters.
Click on image to enlarge.
This 16dB gain is from the differential inputs on the left of fig. 3 to 2-50Ω loads on the amplifier board to the right of fig. 3. This response flatness is paired with the nearly constant group delay through 50Mhz shown in Figure 5. The peak group delay is near the rolloff corner while the intended 50Mhz span is only just past the 2nd major div on the left for this linear frequency sweep.
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Example PLC line driver configuration and MTPR with 100Ω line load
Most PLC line drivers are configured as non-inverting differential gain stages using a Current Feedback Amplifier (CFA) for each of the amplifiers. This allows input impedance isolation for the AFE (and its transmit filter) along with a wide range of gains with the excellent large signal performance intrinsic to the CFA topology. Figure 6 shows the specific design tested here implementing a differential gain of 17.6V/V (25dB) with the relatively low “build out” resistors (3.9Ω) at the output typical of PLC. These resistors strike a balance between the following:
- Isolating the parasitic capacitor of the surge protection diodes (not shown)
- Limiting the insertion loss to the line load
- Limiting any fault current flow beyond that diverted into the protection elements.
Click on image to enlarge.
This is a typical single supply test circuit (+12V) where internal biasing holds the input nodes at mid-supply. Running the target PSD into this producing 15dBm line power with 14.6dB crest factor gives the broadband spectrum of Figure 7. This PSD shows a 30dBm power cutback above 30Mhz.
Click on image to enlarge.
Zooming in on a range of output carriers shows the missing tones (figure 8) with a variable depth below the carriers. This is typical where often a running average of MTPR is used to smooth this variation out. Of course the region above 30Mhz, where the carriers are 30dB lower, will show a stepped down MTPR. Often, those averaged MTPR measurements are normalized by added 30dB back to the actual number in that higher frequency region.
Click on image to enlarge.
Taking the full FFT and forming an 11point running average of these individual MTPR measurements for both the ISL55210 post-amplifier output and then that signal driven into the circuit of figure 6 gives the results of figure 9.
Click on image to enlarge.
These curves indicate the input signal is better than the final performance of the ISL15100. This -50dBc number is typical for broadband PLC driving this relatively heavy 34.6ohm load. This PSD translates into a +/-4V swing on each amplifier output pin (180deg out of phase) for a total differential output swing of 16Vpp across the amplifier output pins of figure 6.
The question now becomes if we add a disabled line driver in parallel with the 34.6ohm load, will it degrade this baseline MTPR from a purely passive load. Early generations of PLC line drivers often added significant non-linearity to the apparent loading whereas more modern devices have improved on this.
Results and conclusions
Showing a lab test system here, a successful characterization of the basic PLC line driver operation has been demonstrated. While challenging, the source signal was generated from a Tek AWG5002B waveform generator and buffered through a combination passive filter + differential I/O gain stage using an ISL55210. This low-level input signal with an MTPR below the target system level was then applied to a modern differential line driver where its load was simply the emulation of 100ohm line load reflected through a 1:1.7 turns ratio transformer down to 34.6ohms. That complex waveform was captured and digitized using a 500MSPS DAQ card using free downloadable PC based “Konverter” software. This yielded an FFT showing approximately -50dBc average MTPR below the PSD step down frequency of 30Mhz.
Part 2 will add a disabled ISL15100 as part of the load and compare its MTPR to the passive load performance measured here. This will then also be compared to some earlier generation PLC line drivers where a clear degradation due to the large voltage swing into a disabled output stage was creating a non-linear load with significant impact on the delivered signals MTPR.
References
- Contact the authors for the data sheet on the ISL15100.
- Ultra Low Power Broadband 8 to 14-Bit Data Acquisition Platform
- 12bit, 500MSPS DAQ users guide
- Low power, 4GHz, ultra low noise FDA
- Contact the authors for this schematic.
About the authors
Raymond Ho is Senior Applications Engineer/High Speed Signal Path and Michael Steffes is Senior Applications Manager/High Speed Signal Path, at Intersil Corp.
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