
Applications including communications, multimedia, server and mobile platforms are expected to benefit. The PCIe v2.0 specification allows operating at the lower speed of 2.5Gbit/s but with more rigorous loop bandwidth characteristics, and targets applications that require PCIe v2.0 compliance but not the 5Gbit/s bandwidth.
Lattice has also worked with Trellisys to provide a PCIe Bus Functional Model, which is expected to overcome the often prohibitive cost of other verification cores that often target ASIC developers. The Trellisys model is able to concentrate on the transaction layer, since typically that is where the user application logic is implemented, by assuming the physical and data links layers encapsulated in the Lattice IP cores have already been verified by Lattice.
For more information, visit www.latticesemi.com/IPSuites
