Low noise silicon quantum dots for more reliable quantum computers
imec in Belgium has shown high quality silicon quantum dots built on 300mm wafers that could lead to more reliable quantum computers.
The spin qubits were built as quantum dots by imec on a 300mm wafer process that is compatible with existing silicon chip production, opening up large scale quantum computer designs.
The silicon spin qubits showed an average charge noise of 0.6µeV/ÖHz at 1Hz, the lowest for a 300mm fab-compatible platform. The low noise values enable high-fidelity qubit control, as reducing the noise is critical for maintaining quantum coherence and high fidelity control.
Being able to make these devices on standard CMOS manufacturing technologies enables wafer-scale uniformity and yield with the required advanced back-end-of-line interconnection of the Si quantum dot structures that are needed for truly large scale quantum chips, with millions or even billions of qubits operating in synchrony.
- Intel has also been working on quantum dot structures for qubits using commercial process technology
The quantum dot spin qubits shown by imec were defined by metal-oxide-semiconductor (MOS) quantum dot structures that resemble modified transistor structures to trap a single spin of an electron or hole.
To achieve long quantum coherence times, the noise, and in particular the charge noise of the quantum dot should be as low as possible. That noise generally results from residual charges, trapped nearby or even inside the quantum dot, removing those is key to increase the performance of the spin qubits.
This is determined by the full processing stack of the quantum dot qubit structure, as any defects introduced there need to be minimized. Industrial manufacturing techniques like subtractive etch and lithography-based patterning have shown to easily result in degradation of the device and interface quality, particularly at the Si/SiO2 interface nearby the quantum dot
qubits.
As a result, it has been difficult to transfer Si/SiO2-based quantum dot structures from the lab to industrial manufacturing. By careful optimization and engineering of the 300mm Si/SiO2-based MOS gate stack, imec achieved the record-low average charge noise across 300 mm wafers, characterized using statistical methods that also showed the main contributors to the noise in the spin qubits.
“We demonstrated charge noise levels that, depending on the source, are between half an order of magnitude to one order of magnitude lower, when compared to current state-of-the-art fab-based Si quantum dot structures and achieved remarkably uniform quantum dot operation,” said Kristiaan De Greve, imec Fellow and Programme Director Quantum Computing at imec. “Our results confirm that 300mm Si MOS is a compelling material platform for quantum dot spin qubits and highlight the maturity of industrial fabrication techniques for qubit development.”
“Knowing the source of the charge noise will give us directions to further optimize the quantum dot structures,. The low-noise qubit environment and demonstrated uniformity of the CMOS manufacturing are just the start of a series of enabling technology developments for upscaling quantum chips towards eventual practical quantum computing, which, with current understanding, will require millions of physical qubits.”
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