Low-noise timing chipset for cellular infrastructure designs

Low-noise timing chipset for cellular infrastructure designs

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By eeNews Europe

The IDT 8V19N4xx chipset is a flexible JESD204B-compliant radio frequency phase-locked loop (RF PLL) and clock synthesiser, designed to meet both the high frequency and low phase noise requirements for 2G, 3G and 4G LTE wireless infrastructure. Using IDT’s FemtoClock NG technology, the low phase noise characteristics enable the system’s analogue-to-digital and digital-to-analogue converters to function with high precision and very low distortion levels. This results in improved signal integrity on transmission and enhanced signal sensitivity on reception, increasing data throughput via lower bit error rates (BER). Reduced noise in the RF signal path enables base-station developers to decrease cost and complexity by relaxing the system’s filter requirements.

Christian Kermarrec, vice president and general manager of the Timing and Synchronization Division at IDT comments, “Our new chipset also offers several key features, such as JESD-compliant clocking and integrated clock jitter attenuation for easy integration into our customers’ specific architectures. The new timing devices complement our industry-leading timing portfolio as well as our performance-leading data converters, data compression, RapidIO, and RF signal chain products for wireless infrastructure applications.”

The IDT 8V19N4xx chipset generates synchronised and highly-configurable clock and SYSREF signals as required by JESD204B applications. This allows designers to use a standard, cost-effective timing chipset with a high degree of flexibility instead of multiple PLLs, synthesisers, and buffers. In addition, the devices feature integrated clock jitter attenuation to simplify system design, and support a low-cost, low-frequency external VCXO to reduce system cost. IDT 8V19N4xx devices come in standard VFQFPN packages.


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