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Low-pin-count 32-bit ARM MCUs in high-volume TSSOP and SO packages target 8/16-bit applications

Low-pin-count 32-bit ARM MCUs in high-volume TSSOP and SO packages target 8/16-bit applications

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By eeNews Europe



Starting at $0.49, NXP’s low-pin-count devices claim to deliver 50 MIPS of performance compared to the 1 to 5 MIPS performance typical of 8/16-bit MCUs, at a highly competitive price point enabled by NXP’s exceptional capacity in manufacturing high-volume commodity packages.

Target applications include human interface devices (HID), consumer electronics, alarm systems, small appliances and simple motor control, among many others.

“Our Cortex-M0 family has grown to become the most complete offering for entry-level 32-bit MCUs, and today we extend it to an unprecedented $0.01-per-MIPS value for traditional 8/16-bit applications,” said Pierre-Yves Lesaicherre, senior vice president and general manager, microcontrollers and logic, NXP Semiconductors. “Shipping over three billion TSSOP and SO packages per year gives us the flexibility and scale to continuously drive towards lower price points and to introduce sub-40 cent 32-bit MCU solutions in 2012.”

“With this introduction we are showing a commitment to drive Cortex-M0 32-bit microcontrollers straight into the 8-bit space,” explained Jan Jaap Bezemer, director of marketing, microcontroller product line, NXP Semiconductors.  “We have been looking to take away the boundaries one by one of traditional 8-bit users to enable them to adopt and embrace 32-bit Cortex solutions. These boundaries really lie in three areas.  One is cost, one is power and one is simplicity. With this announcement we have made tremendous progress on the cost side.  We already had the world’s lowest cost 32-bit microcontroller at 65 cents. But now by introducing SO,TSSOP and DIP packages we can tap into the company’s biggest capacity bracket for high volume, low-pin-count commodity packaging.  That has helped us to further reduce our price points of our 32-bit Cortex-M0 microcontrollers in the market”. 

“Power consumption is very important.  We have been able to achieve over the past few years tremendous improvements in power consumption. Our current Cortex-M0 microcontrollers are best-in-class when it comes to dynamic power. Current products run at 130 μA/MHz which really makes them suitable for low-power applications and that is typically what 8- to 16-bit users expect”.

“The third barrier, which is the one of simplicity, is the one that is most difficult to bring down. The 8/16-bit users have been familiar with those architectures for long time and have become very loyal customers. Cortex-M0 is the simplest ARM core there is and, by design, simplicity was put as the top priority on the list when it was developed.  It only has 56 instructions which makes it very comparable to the number of instructions of traditional 8- and 16-bit architectures and makes it much simpler than some of the 32-bit architectures out there. Providing design tools has also been a major point that drives simplicity. It helps developers to work with these microcontrollers and we have introduced LPCXpresso, which is a new development toolchain to help support this family.  We have made that tool chain very low cost and easy to use”.

“Making another step towards simplicity are the form factor of the SO,TSSOP and DIP packages. They allow for much easier handling, single layer low-cost boards and hand soldering. They are also easier for assembly, prototyping and manufacturing”.

With the world’s smallest 32-bit MCU, the LPC1102, available in a 2-mm x 2-mm Chip-Scale Package (CSP), NXP now claims to offer the widest selection of package options for Cortex-M0 MCUs.

The introduction of the new low-pin-count package options provide reduced footprint and system-cost benefit to customers throughout the product development cycle.  SO and DIP packages provide ease of customer prototyping with the ability to hand-solder, simplifying hardware requirements for programming and debugging.  TSSOP packages eliminate potential reflow process in high-volume production. These easy-to-use and highly reliable packages are popular among 8/16-bit customers and help minimize the number of manufacturing processes while improving yield to further reduce overall system costs. Existing LPC1100 customers can easily convert their designs to the LPC111x low-pin-count devices and reuse their software due to the identical Cortex-M0 instruction set.  The low-pin-count packages are designed for easy PCB layout and scalability by sharing the same pin-out for VDD, VSS, GND, and XTAL.

The LPC1100 series are capable of executing sophisticated algorithms at low power, meeting the ever-increasing demands of cost-sensitive applications that 8-bit microcontrollers struggle to achieve, such as interfacing with sensors and performing complex control tasks. For example, a 16-bit multiply operation performed by an 8-bit microcontroller requires 48 clock cycles at over 770 µA/MHz, while an LPC1100 device can complete the same task in 1 cycle at 130 µA/MHz.

Along with this high performance capability, NXP’s Cortex-M0 LPC1100 family also has numerous innovations in its design:

Timers with PWM generation – For each timer, up to four match registers can be configured as PWM, allowing each timer to support up to three match outputs as single edge controlled PWM outputs.

Dynamic system clock switching – Change frequency on the fly depending on processing demand. The LPC1100 current consumption at 50 MHz is specified at 7 mA. This can be reduced to a little over 130 µA when running at 1 MHz on the low-power internal oscillator.

Clock output – The clock output with divider can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.  The output can source downstream devices such as other microcontrollers, CPLD or FPGA.

Interrupt via any GPIO – Any GPIO pins can be used as Edge- and Level-Sensitive interrupt sources.

Programmable pull up/down/open drain – Internal pull-up/pull-down resistor, pseudo open drain or bus keeper function.

Enhanced GPIO pin manipulation
– Capable of simultaneously reading Bit/Byte/Word or toggling up to 22 I/Os per instruction.

The features will help to accelerate the replacement of 8/16-bit MCUs in many applications. Other key specifications for the LPC111x devices include:

  • Cortex-M0 CPU at 130 uA/MHz, up to 50-MHz CPU clock
  • Up to 4 KB SRAM and 32 KB Flash
  • SPI, UART and I 2 C (Fast-mode Plus)
  • 5-channel 10-bit ADC
  • Two 32-bit Timers and two 16-bit Timers
  • 1% accuracy, 12-MHz IRC
  • Power Profile options via API calls

All NXP Cortex-M microcontrollers are software compatible and offer all the advantages of a single development toolchain. Users can easily migrate their designs between Cortex-M0 and Cortex-M3 with minimal effort. The easy-to-use LPCXpresso IDE for the LPC1100 series is priced under $30.

Recommended distribution unit pricing for 10,000 piece quantities is $0.49 for the LPC1110FD20.  Samples are available in November 2011.

More information about the LPC1100 family of microcontrollers at www.nxp.com/products/microcontrollers/cortex_m0/lpc1100l/

For further information on LPCXpresso and other third-party development tools, see www.nxp.com/lpcxpresso

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