Low-power FPGA solution for PCIe Gen2 at 5 Gbps compliance
The Cyclone V GT passed all PCI-SIG compliance and interoperability tests at the most recent PCI-SIG workshop and is currently included on the PCI-SIG Integrators List. Altera adds that users who need the system performance offered by PCIe Gen2 now have the ability to use a low-power FPGA and lower their total system costs.
Cyclone V FPGAs feature integrated transceivers with data rates up to 5 Gbps and have two hardened PCIe IP blocks embedded within the device. The PCIe 2.0-compliant hard IP blocks consists of the PHY/MAC, data link and transaction layers. The blocks can be configured to function as an end point or a root port and supports up to x4 lanes.
Cyclone V FPGAs and Cyclone V SoCs have a multifunction support feature that allows up to eight PCIe end points to be combined into a single end point while still being supported by standard device drivers. This feature benefits applications such as I/O expansion by reducing software driver development time. The Cyclone V FPGA and Cyclone V SoC are also equipped with Altera’s Configuration via Protocol using PCIe, which allows the hard PCIe core in the devices to operate without the FPGA fabric being loaded. This ensures the PCIe end point is ready for enumeration under the PCIe protocol’s required 100ms specification regardless of the configuration method being used.
Altera solutions include configurable PCIe intellectual property (IP) cores and development boards for endpoint, bridge, switch and root port functionalities. Altera’s Cyclone V GT FPGA Development Kit enables PCIe Gen2 protocol implementation while reducing design risk and shortening development times. The development kit provides a quick and simple approach to develop low-cost and low-power FPGA system-level designs to achieve rapid results.
More information at www.altera.com/cyclone5 and www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html
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