Low power FPGA with hardened PCIe2.0 interface
Lattice Semiconductor has launched a range of small FPGAs with a hardened interface for version 2.0 of the PCI Express standard.
The MachXO5T-NX family is based on the 22nm FDX SOI low power process Nexus platform and provides up to 100K gates of configurable logic, 7.2Mbits of embedded memory and 57Mbits of flash memory.
The interface supports a basic PCIe Gen 2 for machine vision and industrial IoT, providing a 3.3V interface and communications for processors with a lower voltage supply.
It also has up to 291 general purpose I/O that support early I/O configuration and provide added features such as 1.25 Gbps SGMII, default pull-down, hot socketing, and programmable slew rate for simplified board design. There is also on-chip multi-boot with bitstream encryption (AES256) and authentication (ECC256) for more secure designs.
“As the pace of technological innovation accelerates and system management designs become more complex, the need for advanced processing capabilities increases,” said Dan Mansur, Vice President, Product Marketing, Lattice Semiconductor.
“Lattice MachXO5T-NX FPGAs equip our customers with more capacity, faster I/O, and enhanced security features in the low power, small size envelopes to help them simplify system integration while maintaining power efficiency, compatibility, and performance.”
MachXO5T-NX FPGAs are sampling today and are supported by the latest release of Lattice Radiant® design software.
www.latticesemi.com/en/Products/FPGAandCPLD/MachXO5-NX
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