The 3D stack resembles as close as possible to future commercial chips. It consists of imec’s proprietary logic CMOS IC on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps. Heaters were integrated to test the impact of hotspot on DRAM refresh times. And, the chip contains test structures for monitoring thermo-mechanical stress in a 3D stack, ESD (electro-static discharge) hazards, electrical characteristics of TSVs and micro-bumps, fault models for TSVs, etc.
Imec’s 3D integrated DRAM-on-logic demonstrator showed that a minimum die thickness of 50µm is required to deal with local hot spots on the logic die, which are generated by local power dissipation. Due to the strongly reduced lateral heat spreading capability of thin die, these hot spots are higher in temperature and more confined if the die thickness is reduced.
The hot spots on the logic die cause local temperature increases in the memory die. This may cause a reduction in retention time of the DRAM devices. However, imec’s 3D stacked demonstrator has proven that the DRAM may not be thermally isolated from the logic die since the DRAM die also acts as an effective heat spreader for the logic die. As such the intensity of the hot spot is reduced and thereby the temperature rise in the DRAM device is strongly limited.
The results of the various experiments allowed us to calibrate our thermal models which are implemented in 3D EDA tools. They have proven to be valuable means to design next-generation 3D stacked ICs. The design of the 3D chip is realized together with many players in the 3D integration supply chain.
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