Lower power MRAM targets for embedded designs

Lower power MRAM targets for embedded designs

Technology News |
By Nick Flaherty

Reneas Electronics reports a 72 percent reduction in write energy and a 50 percent reduction in the voltage application time in benchmarks using a 20Mbit test chip built in a 16nm FinFET logic process.

The STT-MRAM is already a non-volatile memory for storage but these additional reductions in energy consumption will help with reduced power consumption in microcontroller units (MCUs) used in endpoint devices. This will further promote the adoption of STT-MRAM over flash memory as an embedded memory option.

The first technique is to introduce a pulsed writing scheme that is automatically and adaptively terminated in response to the write characteristics of each memory cell.

The second technique is to optimize the number of bits, to which write voltage is applied simultaneously.

The writing scheme is an adaption of past fixed-voltage schemes. Instead of applying a fixed voltage during write operation where the MTJ changes from HRS to LRS in a conventional self-termination write, a slope voltage that rises gradually over time has been adopted. This makes it possible to detect write completion stably and consistently. Even when the memory cell current does not reach the detection level of the detector circuit immediately after state transition due to variation in memory cell characteristics and other factors, the subsequent gradual rise in the write voltage increases the memory cell current. This eventually exceeds the detection level, enabling the completion of the write to be detected and application of the write voltage to be halted.

During write operation where the state transition is in the opposite direction, from LRS to HRS, the memory cell current changes from a large to a small current, so write completion detection using a slope voltage pulse is not possible. Therefore, a current source circuit is used to increase the write current in a sloping manner, and write completion is detected by monitoring the write voltage with a voltage detector circuit to determine if it exceeds a pre-set judgement voltage.

Previously, the MRAM write voltage was determined based on the worst bit-write characteristics in the memory cell characteristics variation. This meant that a high write voltage was necessary, and a charge pump circuit was used to generate it. To keep the current requirements down the memory array was divided into multiple sub-zones and each written to sequentially increasing the right time.

Renesas focused on the fact that the write voltage could be reduced substantially by allowing write failure bits of up to 10 percent. A higher voltage is then used only to write to the remaining 10 percent of bits.

Since write voltage application completes in two phases with this technique, the overall write voltage application time can be reduced by 50 percent or more compared to the conventional method of dividing the write unit into four or more groups.

Renesas presented the work at the 2021 IEEE International Electron Devices Meeting (IEDM)

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