Lowest jitter clock chip is Synchronous-Ethernet compliant

Lowest jitter clock chip is Synchronous-Ethernet compliant

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By eeNews Europe

Offered as the lowest jitter, lowest power and most frequency-flexible timing solution for high-speed networking equipment based on the Synchronous Ethernet (SyncE) standard, the Si5328 has a combination of any-frequency synthesis and industry-leading jitter performance (as low as 263 femtoseconds RMS). The precision clock multiplier and jitter attenuator addresses the need for ultra-low jitter physical layer reference clocks in Carrier Ethernet switches and routers. At 20% of the size and power of competing SyncE clocks, the Si5328 provides a SyncE-compliant timing solution for edge routers, multi-service switches, wireless backhaul systems, DSLAMs and GPON/GEPON optical line termination (OLT) equipment.

The telecom infrastructure market is rapidly transitioning from legacy SONET/SDH networks to higher-speed, more cost-effective Ethernet networks. A key enabling technology behind this network transition is Synchronous Ethernet, which is used to distribute accurate timing in Gigabit Ethernet (GbE), 10 GbE, 40 GbE, and 100 GbE Carrier Ethernet switches and routers. Every Carrier Ethernet switch and router requires a high-performance SyncE clock to provide wander filtering, distribute timing and provide a low-jitter Ethernet PHY reference clock. Silicon Labs has addressed this application need with the industry’s lowest jitter, most frequency-flexible SyncE timing solution optimized for Ethernet PHYs ranging from GbE to 100 GbE.

The Si5328 is fully compliant with ITU-T G.8262 SyncE clock requirements including EEC Options 1 and 2. When paired with a Stratum 3 temperature-compensated crystal oscillator (TCXO), the Si5328 meets all of the jitter, wander and holdover requirements specified by the SyncE standard. With its integrated loop filter featuring selectable loop bandwidths (0.1 Hz and 1 to 10 Hz), the Si5328 can be designed into any networking system that must comply with SyncE specifications. This integration eliminates the need for expensive discrete timing card phase-locked loops (PLLs) in some systems and provides manufacturers the assurance that their networking products can be deployed worldwide by their end customers.

Building on Silicon Labs’ DSPLL technology, the Si5328 SyncE clock can generate any output frequency ranging from 8 kHz to 808 MHz and from any input frequency from 8 kHz to 710 MHz. This frequency-flexible any-rate capability enables networking system designers to synchronise to, and generate, virtually any legacy telecom or SyncE frequency, simplifying system designs from GbE to 100 GbE. The Si5328 can be digitally reconfigured through I2C or SPI interfaces without the need for bill of materials (BOM) changes.

The Si5328 clock’s high level of single-chip integration greatly simplifies PCB design. Its DSPLL architecture eliminates the need for external crystal and loop filter components, reducing PCB area while also maximising immunity to board-level noise. Selectable output signal formats (LVPECL, LVDS, CML and CMOS) ease interfacing with popular Ethernet transceivers and eliminate level shifters and other filtering components. Powered by a single 2.5 or 3.3 V supply, the Si5328 operates without the need for multiple power supplies and discrete filtering.

The Si5328C-C-GM supports clock outputs up to 346 MHz and is priced at $7.50 (10,000); the Si5328B-C-GM supports clock outputs up to 808 MHz and is priced at $9.38 (10,000). An evaluation platform, the Si5328-EVB evaluation board, is priced at $250.

Silicon Labs;

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