EDA and intelligent system design provider Cadence Design Systems has announced the first LPDDR5X memory interface IP design optimized to operate at 8533 Mbps — up to 33% faster than the previous generation of LPDDR IP. LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking.
The company’s LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements. The solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyzer.
“Cadence LPDDR5X IP operating at 8533Mbps in silicon showcases Cadence’s next-generation architecture for complete memory system IP solutions,” says Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “This new leading-edge memory IP solution solidifies our memory interface IP leadership by enabling the industry’s future AI, automotive and mobile SoC designs today.”