Making HDTV in the car reliable and secure
High definition video, fast becoming the de facto standard within the home is now available in the automotive market. We expect the same viewing experience in the car that we have become accustomed to at home, and children want to watch their favorite Blu-ray discs on long journeys. Video distribution throughout an automobile is a considerable challenge to automotive infotainment system developers, especially at the signal bandwidths needed to support high defintion video content. Integrated circuit technologies that can handle the required data rates, reduce expensive cabling and connectors, and mitigate electromagnetic interference (EMI) problems are in great demand.
National Semiconductor (in the meantime acquired by Texas Instruments) recently released the industry’s first Ser/Des chipset with on-chip high-bandwidth digital content protection (HDCP) for automotive infotainment systems. The FPD-Link III chipset enables secure distribution of encrypted video and audio content, such as Blu-ray movies up to 720p resolution, to create a home theater experience in the vehicle. In addition it also supports a uniquely architected full duplex bi-directional control channel that enables real time touch screen applications. The chipset allows video and audio data, clock and control signals to be serialized and transmitted over a single differential wire. This article describes the system benefits brought about by this technology, and other enhanced features that reduce EMI and total system cost. The simplified block diagram in figure 1 shows how multiple wires are replaced by a single differential pair.
Figure 1: FPD-Link III Simplified System Block Diagram
The third generation FPD-Link chipset described here consists of the DS90UH925Q serialiser and DS90UH926Q deserialiser. The DS90UH925Q converts video, digital I2S audio and control signals from the head unit processor (graphics processor, camera or Blu-ray/DVD player) into a serialized stream for distribution through the vehicle’s cable harness. The DS90UH926Q converts the serialized information stream back into video, audio and control outputs to drive central information and rear passenger seat displays.
The consolidation of video data and control over a single differential pair reduces interconnect size, weight and cost. In addition to eliminating the expense and weight of additional cabling and control connectors such as CAN, LIN, or I2C, the full duplex bidirectional control channel allows control signals to be sent from the display to the host processor independent of video blanking periods. This is illustrated in figure 2. This full duplex low latency implementation is a significant improvement over approaches which transmit control data only during video blanking periods or those which modulate the common mode signal.
Such methods result in indeterminate latency undesirable in touch screen applications, and EMI issues. The chipset serially routes 24-bit color video content over distances in excess of 10 meters and supports a pixel clock range from 5 MHz to 85 MHz. This enables infotainment system designers to develop a modular platform supporting a wide range of video sources and displays for deployment across their entire range of vehicles.
Figure 2: Control data sent independent of video blanking periods. Common mode signal not modulated
On-chip HDCP
HDCP is a form of digital copy protection developed by Intel Corporation to prevent copying of digital audio and video content over commonly used interfaces between digital media devices and displays. Texas Instrumentsis a HDCP adopter meaning that it has obtained a license from Digital Content Protection LCC (DCP) to develop HDCP supporting technology. National has obtained a unique set of keys which are loaded into on-chip non-volatile memory during the manufacturing process and which are not accessible externally. Each HDCP capable device has a unique set of 56-bit keys.
During authentication, the serialiser and deserialiser exchange their keys under a procedure called Blom’s scheme. The exchanged keys are combined and used to encrypt and decrypt data. Encryption is done by a stream cipher. The cipher function is implemented in both the serialiser and deserialiser. The encrypted data is transmitted over the FPD-Link III interface and is decrypted by the deserialiser. The embedded HDCP processing capability simplifies infotainment system design and eliminates the need for costly secondary components, such as microcontrollers and FPGAs, by handling the computationally intensive tasks of data authentication and encryption.
EMI mitigation
Passive EMI reduction measures through metal shielding and capacitors are not the preferred option due to cost and weight constraints. System designers prefer active EMI reduction through the use of embedded chip technology. EMI is minimized in the FPD-Link III chipset by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
Randomization, Scrambling and DC Balancing are commonly used techniques to reduce EMI and won’t be described here. Spread-spectrum clock generation (SSCG) is another technique used to reduce EMI spectral density as is shown in figure 3. Due to its periodic nature, a clock signal has an unavoidably narrow frequency spectrum.
Signal energy is concentrated at its fundamental frequency and harmonics, resulting in a frequency spectrum that can exceed the regulatory limits for electromagnetic interference. Spread-spectrum clocking avoids this problem by reducing the peak radiated energy, effectively by modulating the clock fundamental frequency. The technique reshapes the system’s electromagnetic emissions to comply with electromagnetic compatibility (EMC) regulations. SSCG does not reduce the total energy radiated by the system, but distributes the energy so that it is spread over a larger frequency band, without putting enough energy into any one band to exceed the statutory limits.
The DS90UH925Q serializer and DS90UH926Q deserializer are capable of tracking an input spread spectrum clocking (SSC) profile up to 35 kHz modulation at 85 MHz. The DS90UH926Q provides an internally generated spread spectrum clock generator to modulate its outputs. Both clock and data outputs are modulated. Up to 100 kHz modulation is supported. This feature may be selected and controlled through the I2C interface. Measurements on an EMSCAN flatbed scanner using evaluation boards not optimized for EMI performance show than enabling SSCG in the deserialiser improves radiated emissions and peak harmonics by up to 10dB. This is illustrated in figure 3.
Figure 3: EMI Emissions and Peak Harmonics Reduction Due to SSCG
Advanced video processing capabilities – White Balancing and Dynamic FRC Dithering
The chipset supports advanced processing techniques for image enhancement that improve user experience and reduce total system cost. In image processing, colour balance is the global adjustment of the intensities of the primary colours (red, green, and blue – RGB). The general method is sometimes called gray balance, neutral balance, or white balance. White balance changes the overall mixture of colours in an image and is used for colour correction. The DS90UH926Q has a white balance feature that enables similar display appearance when using LCD’s from different vendors. It compensates for native colour temperature of the display, and adjusts relative intensities of RGB to maintain specified colour temperature.
Programmable control registers are used to define the contents of three gamma Look Up Tables (LUTs) – 8-bit per colour (RGB) value. The LUT maps input RGB values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8-bits per entry with total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. This Feature may also be applied to 18-bit color applications when only 6- bit RGB data is entered into LUT.
The Dynamic FRC (Frame Rate Control) Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB to 18-bit RGB, smoothing colour gradients, and allowing the flexibility to use lower cost 18-bit displays. It converts 24-bit RGB data (8 bits per sub-pixel) to 18-bit RGB data (6 bits per sub-pixel) using HiFRC (High Frame Rate Control) scheme. HiFRC is a novel dithering algorithm for high colour depth and high colour performance. The least two LSBs of the 8-bit gamma entries are truncated. It dynamically adjusts the dithering algorithm to optimize performance and minimize artifacts. This feature can be enabled through an I2C register.
Further details on Texas Instruments’ FPD-Link III technology can be found at https://www.ti.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
