Marvell, TSMC team on N5P 5nm data centre chips

Marvell, TSMC team on N5P 5nm data centre chips

Business news |
Marvell has extended its deal with TSMC to cover chips for the data infrastructure and automotive markets using enhanced 5nm N5P technology.
By Nick Flaherty

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The 5nm N5P enhanced process gives a 20 percent performance improvement or 40 percent power reduction over the 7nm process, which is key for reducing the thermal challenges in the data centre.

Marvell’s 5nm portfolio will provide the essential high-performance compute, networking and security technology for a wide range of end-market applications in the data centre. This will be used for Ethernet chips that enable high-performance, low-power network connectivity, optimized for applications that span cloud data centers to the harsh environment of the automotive market.

Marvell will also use the 5nm process for its OCTEON ARM-based procesors for embedded infrastructure applications targeting a wide variety of wired and wireless networking equipment including switches, routers, secure gateways, firewalls, and network monitoring solutions. OCTEON is the world’s most widely deployed data processing unit (DPU) for data-centre scale computing and enables a multitude of acceleration and offload capabilities, including Smart NICs and security accelerators.

The IP is also available to its ASIC design business on 5nm: MARVELL’S ASIC BUSINESS SHAKEUP

With multiple designs already under contract for its 5nm portfolio, Marvell is developing designs across the carrier, enterprise, automotive, and data centre markets with first products sampling by the end of next year as TSMC’s 5nm process reaches volume production at its Fab 18. This is a significant milestone for the infrastructure industry as the process node cadence now closely follows that of the consumer and high-performance market.

The 5nm N5P designs are supported by an IP portfolio that covers the full spectrum of infrastructure requirements including high-speed SerDes up to 112Gbps long-reach, processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces. These technologies and more are all in development now on TSMC’s N5P process, an enhanced version of TSMC’s 5nm technology which delivers approximately 20 percent faster speed or 40 percent power reduction compared to the previous 7nm generation.

“We are proud to partner with Marvell to serve the data infrastructure market with cutting-edge silicon, and are committed to supporting their growing needs in development, quality, supply and capacity,” said Dr Kevin Zhang, Senior Vice President of Business Development at TSMC. “In the 5G era, more applications than ever are demanding the most advanced silicon technology we can provide. We look forward to collaborating with Marvell to meet these demands with our combined design and process expertise and extend our long history of partnership to the 5nm generation and beyond.”

“Now is the time to invest in data infrastructure – the world is relying on us – and our customers are depending on us,” said Raghib Hussain, Chief Strategy Officer and Executive Vice President of the Networking and Processors Group at Marvell. “TSMC’s 5nm process provides world-class power, performance and gate density – and it’s critical for the demands of the leading companies in the world in cloud, 5G, enterprise, and automotive. We’re thrilled to have a strategic partner like TSMC to help us continue to push the boundaries of innovation possibilities.”

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