Maskless exposure to slash costs of back-end lithography

Maskless exposure to slash costs of back-end lithography
Technology News |
Wafer bonding and lithography equipment provider EV Group (EVG) has unveiled a maskless lithography technology specifically developed for the back-end lithography requirements of advanced packaging, MEMS, biomedical and high-density PCB applications.
By eeNews Europe

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Dubbed MLE (for Maskless Exposure), the technology is said to be scalable for high-volume manufacturing, combining a patterning resolution better than 2µm in any arbitrary direction with digitally programmable layouts that eliminate the significant overhead costs associated with photomasks.

MLE technology accommodates any wafer size up to panels, supporting full-resolution, stich-free dynamic photoresist patterning while compatible with all commercially available resists through a tightly integrated clustered write-head configuration and multi-wavelength high-power UV source.

The digitally programmable maskless exposure also bring unprecedented flexibility, enabling individual die annotations (serial numbers, encryption keys, etc.) with extremely short development cycles for new devices. The MLE is unaffected by substrate deformation and warpage and is consumables-free.

Throughput is independent of layout complexity and resolution, and MLE achieves the same patterning performance regardless of photoresist. The new MLE lithography technology complements EVG’s existing lithography systems, targeting new and emerging use cases where other approaches face scalability, cost-of-ownership and other limitations.


The company is working on the integration of MLE into a new line of systems. It sees heterogeneous integration as a driving force for such back-end lithography, especially for advanced packaging, where the minimum resolution requirements for redistribution layers and interposers are becoming increasingly stringent, sometime exceeding two microns.

Die placement variation and the use of cost-efficient organic substrates require more flexibility in patterning and designers call for higher overlay accuracy as well as high depth of focus in vertical sidewall patterning. Minimizing pattern distortion and die shift due to wafer distortion in fan-out wafer level packaging (FoWLP) and support for thick and thin resists, are just some of the criteria for existing and future advanced packaging lithography systems.

The system can be scaled according to user needs by simply adding or removing UV exposure heads, so it can process a range of substrates from small silicon or compound semiconductor wafers up to panel sizes.

EV Group – www.EVGroup.com

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