Measuring 2 nV/√Hz noise and 120 dB supply rejection in linear regulators; the Quest for Quiet, part 1
A quiet, well regulated supply is important for optimum performance in a number of circuit applications. Voltage controlled oscillators (VCOs) and precision voltage controlled crystal oscillators (VCXOs) respond to small changes in their supply very quickly. Phase-locked loops (PLLs) require a stable supply, as signal on the supply translates directly to phase noise in the output. RF amplifiers require quiet supplies, as they lack the ability to reject supply variations, and regulator variation will appear as unwanted side bands and lower the signal-to-noise ratio. Low noise amplifiers and analogue-to-digital converters (ADCs) do not have infinite supply rejection and the cleaner the regulator output is, the higher their performance.
Once fully built, one can determine if the supply has low enough noise for the application. Oscillator phase noise is measured and compared against results achieved with a known good supply, ADCs are checked to ensure they are getting the maximum number of bits. These are tricky, time consuming measurements and it would be better to make sure the noise levels are low enough for your needs without expensive trials.
In addition to noise, one must also consider the supply rejection capabilities of the linear regulator. Poor rejection from a linear regulator will bring switching regulator residue or other unwanted signals through, corrupting the hard work done to ensure a clean supply. Extremely low noise from the regulator is worthless if poor supply rejection brings enough signal through to swamp noise levels.
Measuring output voltage noise: being Quiet is Nothing New
The subject of noise has been broached before. Linear Technology Application Note 83, “Performance Verification of Low Noise, Low Dropout Regulators,” published in March 2000, describes in detail a method for measuring output voltage noise of regulators down as low as 4 µVRMS with confidence. The amplifier circuit and filters in the Application Note gave 60 dB of gain across a 10 Hz to 100 kHz bandwidth. This is a good starting point to determine confidence in measurement of noise levels.
New linear regulators such as the LT3042 are now in production with much lower output voltage noise levels. While the family of regulators released around the publication of Application Note 83 operate with approximately 20 µVRMS noise in the 10 Hz to 100 kHz band, the LT3042 is now available with noise levels as low as 0.8 µVRMS across the same frequency band. Reviewing the circuit from Application Note 83 shows an input referred noise floor of 0.5 µVRMS, which provides less than 1% error when measuring noise levels as low as 4 µVRMS. With output noise levels of 0.8 µVRMS, this noise floor is now unacceptable; the regulator itself operates at noise levels only slightly above the measurement circuit. This translates to almost 20% error, making the measurement circuit too significant a factor to be able to measure signals with confidence.
Measuring less than 1 µVRMS noise is not a trivial task. Working backward from a 10 Hz to 100 kHz measurement band, this equates to a noise spectral density of 3.16 nV/√Hz (assuming white noise). This is equivalent to the Johnson noise of a 625Ω resistor! Measuring noise at these levels within 5% requires that instrumentation have an input referred noise of 1 nV/√Hz; measuring within 1% requires input referred noise of 450 pV/√Hz.
next; What to measure?…
What measurement to make?
We now have an idea of the noise floor required by instrumentation, but there is a question as to what frequency range is critical and what instrument is to be used to measure the resultant noise. To measure noise spectral density, the regulator output can simply be fed through low noise gain stages [Ref. 1] and then fed into a spectrum analyser, blocking out unwanted frequencies from measurement. If peak-to-peak or RMS noise is desired, then band stops are warranted on the low noise gain stages to ensure that only signal in the desired bandwidth is measured.
A commonly used broadband noise measurement frequency range is 10 Hz to 100 kHz. This encompasses the audio frequency band and ensures minimal side bands for baseband data transmitted over RF. Low noise regulators used in phase-locked loops and high accuracy instrumentation require higher frequency measurements (up to 1 MHz and beyond), so we should not limit ourselves to only the 100 kHz range. Ideally, band stops would be absolute brick-wall filters at the desired frequency, but the realities of circuit design prevent us from achieving this. Higher order Butterworth filters are selected to maintain maximum flatness in the range of the frequencies of interest as well as their ability to give a better brick-wall approximation. The order of the filter is determined by the error introduced by their equivalent noise bandwidth (ENB): a second-order low pass Butterworth has an ENB of 1.11fH, which is too high an error. Fourth-order filters drop the ENB to 1.026fH, which gives error levels of approximately 1.3%. Higher order filters would add unnecessary complexity and cost while accomplishing minimal improvement in performance. Fourth-order filter error is coupled with errors introduced by the input referred noise, indicating that a measurement within 5% requires that input referred noise of the amplifier be targeted to contribute no more than 1% maximum error.
Circuit gain must be considered as well. If the gain is too low, noise of the measurement device will sum in and corrupt measurements the same as input noise of the amplifier. At the same time, instrumentation may not be sensitive enough to provide reliable results. For RMS noise measurements, an HP3400A RMS voltmeter has a bottom range of 1 mV, so 60 dB is an absolute minimum gain. Based on the noise floor of spectrum analysers currently commercially available (and available from the secondary market), it was decided that 80 dB would work best.
Regulator measurement considerations
Figure 1. Architecture of the noise measurement circuit. (Click here to download higher-resolution version)
A block diagram of the noise measurement circuit is shown in Figure 1. Initial DC blocking is followed by an ultralow noise gain stage to amplify the input by AV = 25. Following this is a 5 Hz single order high pass to another gain block with AV = 20. This is followed by a 10 Hz second-order Sallen-Key filter and one last stage of gain at AV = 20 bringing net gain to 10,000, or 80 dB. This is followed by one of three selectable outputs depending on the high end frequency desired; available are a 1 MHz limit, the 100 kHz band stop discussed earlier, and a wideband output that operates to the limits of the gain stages used (the –3 dB frequency is measured at 3 MHz). Each output is followed by one last 5 Hz high pass filter to block any residual DC.
next; the actual circuit…
Figure 2. Full circuit of the noise measurement scheme. (Click here to download higher-resolution version)
The actual circuit follows in Figure 2. Here, the DC blocking is shown as a 680 µF capacitor followed by a 499Ω resistor. The capacitance and resistance values chosen are one of the major trade-offs in the circuit. The resistor must be low enough in value so that the base currents of the following stage will not cause significant DC error. But if too low a value is chosen, the capacitance required in the filter becomes extremely large. A low resistor value also may allow the filter to become part of the frequency compensation for the regulator under test, changing the results measured. The current values form a 0.5 Hz high pass filter.
The architecture of the first gain stage is critical. This stage must provide fixed gain while operating with extremely low input referred noise. Based on previous work done by the late Jim Williams in [Linear Technology] AN124, “775 Nanovolt Noise Measurement for A Low Noise Voltage Reference,” a differential transistor pair driving the inputs of an op amp was chosen to give best bandwidth while still providing low noise. Operating the differential pair at a gain of approximately 80 means that the noise of the transistors dominates and op amp noise is not a significant factor.
The ultralow noise amplifier first stage is formed by two matched pairs of THAT300 transistors in parallel (to lower input-referred noise) followed by an LT1818 configured to give a total gain for the stage of 25. The THAT300 transistors come as four devices in a single SO-14 package and offer good matching characteristics (typical 500 µV ∆VBE) and typical 800 pV/√Hz noise. The LT1818 was chosen for the high gain-bandwidth product.
Paralleling of input pairs and amplifier stages provides a benefit in terms of noise floor without sacrificing gain. Amplifier circuits are known to show a drop in voltage noise when paralleled, with N stages giving a √N reduction in noise. Paralleling of the transistor pairs lowers the effective noise back to 800 pV/√Hz. This noise is then further reduced by paralleling four of the full input stages together for another noise reduction of 2X to 400 pV/√Hz. Subsequent addition of noise sources is minimal, allowing us to be close to the 450 pV/√Hz desired for 1% accuracy.
Following the first stage, 330 µF capacitors and 100Ω resistors provide DC blocking of any offsets that are inherent to the differential transistor pair and op amp. These also provide a 5 Hz highpass filter, helping to create the desired low frequency band stop. All four input stages are summed together into a second stage with a gain of 20. As the input has already been amplified at this point, the op amp noise is again a small factor.
The 10 Hz second-order high pass is a simple unity-gain Sallen-Key filter; an increase in the Q of this filter is used to help offset the frequency response of the single 5 Hz high pass stages and give a 3 dB point of 10 Hz for the total circuit. Again, the DC blocking of this stage prevents any offsets that may have been amplified in the previous stage from being subjected to additional gain. Failure to block DC between various stages could lead to driving amplifiers to the rails and invalidating measurements. Each stage of gain has been interspersed with a filter to prevent DC from getting through while providing the low end band stop at the same time.
The last stage is a simple inverting amplifier with adjustable gain to compensate for variations in component values. From here, the circuit splits into three output stages. The highest bandwidth comes straight from a follower avoiding low pass filtering, giving the maximum 3 MHz bandwidth for noise throughput at full gain. The second output has a 1 MHz fourth-order Butterworth low pass filter, and the final output features a 100 kHz fourth-order Butterworth low pass filter. All three stages use one final DC blocking RC filter at 5 Hz.
Part 2 of this article will continue with a discussion of critical Component Choices
Todd Owen and Amit Patel are Senior IC Design Engineers, at Linear Technology.
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