Memory compiler targets 40nm ultra-low-power process for IoT

Memory compiler targets 40nm ultra-low-power process for IoT

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By Graham Prophet

The 40nm ULP compiler supports synchronous single port SRAM with operating voltages ranging from 0.6 to 1.21V and memory capacities ranging from 8 kBytes to 576 kBytes with maximum word lengths of 72 bits. Previous test chip results revealed an up to 80% savings in dynamic power consumption and up to 75% reduction in static power.


The design targets power-critical “keep alive” IoT, wearable and medical applications. The SRAM itself is single rail and DVFS compatible. A suite of power management options include light sleep, deep sleep and power-down modes. The array is subdivided into up to eight banks that can be in independently active, retained or powered off modes. The compiler also provides Design-for-Test (DFT) and BIST support.


The sureCore low power SRAM IP is applicable to a variety of IoT, wearable and medical applications that mandate keep-alive memory. It enables automated spoken word or phrase recognition and over or under temperature events.


sureCore’s Ultra Low power SRAM enables computing at formerly unattainable low voltages levels of 0.6V. By combining low voltage operation with the leakage characteristics of the underlying process, sureCore has created an SRAM that supports operating speeds down to 20 MHz (at 0.6V) and exceeds 300 MHz at 1.1V.


“The 40nm ultra-low power process technology is, arguably, the cost effective sweet spot for many IoT, wearable and medical applications where long battery life is must,” said Paul Wells, sureCore’s CEO. “Mature nodes such as 40nm represent a sweet spot for IoT technical and business challenges and the sureCore Ultra Low power SRAM is quickly being acknowledged the leading power critical solution.”


The company also has a 28nm FDSOI compiler and is currently working on a 22nm FDSOI Compiler, seeing that technology as another popular IoT node.






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