Memory compliance solution debugs protocol timing violations via logic analyzer

Memory compliance solution debugs protocol timing violations via logic analyzer

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By eeNews Europe

The B4661A memory analysis software has a performance analysis option that provides powerful new trace overview and navigation features. The memory analysis software also offers DDR and LPDDR decoder options. With this software and a Keysight logic analyzer, digital designers can monitor DDR3/4 or LPDDR2/3/4 systems to identify elusive violations in protocol or bus-level timing.

The memory analysis software includes four options:

  1. DDR decoder with physical address trigger tool;
  2. LPDDR decoder;
  3. DDR and LPDDR compliance violation analysis;
  4. DDR3/4 and LPDDR2/3/4 performance analysis.

The DDR decoder covers DDR/2/3/4 and provides protocol decoding of memory transactions using a Keysight logic analyzer. The protocol-decoding software translates acquired signals into easily-understood colorized bus transactions showing associated data bursts for double-edge data rate captures. The Keysight U4154B logic analyzer is already proven to capture DDR4 at 3.3 Gbps using the FS2510AB DDR4 DIMM interposer from a Keysight channel partner, FuturePlus Systems. The logic analyzer solution is ready to capture higher data rates when DDR4 standards incorporate higher data rates.

Using the LPDDR decoder, engineers can decode valid read and write commands to include row and column addresses and the complete data burst associated with the command. Keysight U4154B logic analyzers are proven to capture LPDDR4 at 3.2-Gb/s data rates.

Using the DDR3/4 and LPDDR2/3/4 performance analysis tool, navigation to problem areas is simplified with a powerful new traffic overview that presents the logic analyzer trace capture at a high level with user-selected filtering.

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