Memory design for autonomous driving systems

Memory design for autonomous driving systems

Feature articles |
By Peter Clarke


While most industry watchers believe we are still perhaps over a decade away from fully autonomous vehicles becoming common in European cities, vehicle automation is already a hot spot of design activity.

The automotive industry, its regulators and insurers, unite the various technologies for automating vehicles under the banner of Advanced Driver Assistance Systems (ADAS). They categorise system capabilities into six levels, between level 0 (L0), where the vehicle is being driven by a human with no assistance, and level 5 (L5), full autonomy, where no human attention or intervention is required for the vehicle to drive safely.

ADAS L1 capabilities such as cruise control are considered standard specification for many automotive brands. ADAS L2, partial automation, and the initial L3, conditional automation, systems are on the market.  Audi’s 2018 A8 is one of a few vehicles marketed as having L3 ADAS capabilities; on roads with a central barrier, at speeds below 60Km/h, its ‘Traffic Jam Pilot’ mode can take full control.

The journey to full autonomous driving, ADAS L5 is still under way. In this article, we consider the demands of memory subsystems at the higher ADAS levels, exploring the impact of memory technology choices to identify the current design sweet spot between performance and practicality.

Growing ADAS Memory Bandwidth Demands

Above the most basic ADAS levels, vehicles will require multiple sensors to be integrated to enable the timely and accurate decision making required for safe automated driving.  Typically multiple LiDAR, radar and camera sensors at the front, rear, left, and right of the vehicle will be employed to compose a 360-degree view for situational awareness. Both wide-angle sensors for short range detection of objects, and longer range sensors with a narrower view are usually required.

Analysis from just three years ago, estimated that a comprehensive sensor suite comprising radar, LiDAR, cameras, ultrasonic, vehicle motion, satellite navigation and an inertial measurement system, would require a total sensor bandwidth of around 40 gigabits per second (Gb/s). 

In the intervening period, LiDAR, radar and camera, resolutions have climbed to match the performance requirements of more demanding ADAS levels and a broader range of operating conditions. Recent radar sensor packages alone are delivering 30 Gb/s, each of these would be only a portion of the data flow generated by the complete sensor suite.

This growing body of collected sensor data feeds the machine learning (ML) training systems of neural networks, to produce increasingly complex inference models for the various aspects of vehicle control. Inference models with the sophistication required to deliver full autonomy, L5, will require significant bandwidth between memory and processing elements to synthesise, analyse and act on the real-time sensor data flooding into the system.

ML training efficiency is limited by how much data can be processed. It can be accelerated by scaling into data centre-based systems to deliver the necessary storage, bandwidth and compute capacity. With the exponential growth in the size and complexity of training models, that training scaling comes with its own set of challenges. The data centre environment however is far different from what ADAS systems will experience in-vehicle.

In-vehicle inference requires compute-intensive, high-bandwidth systems delivered within cost, space and long-term reliability constraints that don’t apply to data centre hosted ML training environments. So while both training and inference are ML processes, each brings its own set unique demands for memory system selection.

In-vehicle delivery of the data throughput needed for real-time inference at full autonomy will require significant optimisation of memory-processor interfacing whether using CPU, GPU or a dedicated AI/ML accelerator platform.

Figure 1: Predicted memory bandwidth required by each ADAS Level (Image source:

The size and complexity of inference models grow significantly with each upward step in ADAS level, with a consequent increase in the required memory-processor bandwidth. An L2 ADAS, system in current use is likely processing around 60 gigabytes per second (GB/s). The step up to L3 ADAS, with inputs from a more sophisticated sensor suite, will require at least 200 GB/s of memory bandwidth. So how can this bandwidth be practically delivered in vehicle?

Memory choices

As a safety critical system ADAS has high qualification standards. To reduce both design risk and in service risk, tried and tested memory systems are preferred. Technologies such as LPDDR with billions of smartphone deployments, DDR4, used most commonly in laptops and desktop systems, and GDDR6 designed into in hundreds of millions of graphics cards, have been favoured for implementation in ADAS systems. Table 1 summarises the characteristics of these memory systems.






Bandwidth (GB/s) per device

Low-Medium (17)

Medium (25.6)

Medium (25.6)

High (64)

Data Rate (Gb/s)





Interface width (bits)





Board Area / System design





Efficiency (mW/Gb/s)

High (3)

High (3)

Moderate (10)

Moderate (10)

Cost ($)





Reliability / Yield





Table 1: Memory system technology characteristics. Source: Rambus

Architectural options memory in L3 ADAS, and higher.

Figure 2, below, shows options for memory systems capable of delivering 224 GB/s, using these memory technologies. This exceeds the minimum bandwidth threshold of 200 GB/s expected to be required for a realistic L3 implementation.

DDR4 is not shown, it would be impractical in a realistic design. With a 32-bit bus DDR4 would require space for 18 DRAM devices.

LPDDR4, with 13 DRAM devices required would still consume significant board and die area, making it a challenge to implement from both a routing and cost perspective.

Figure 2: L3 ADAS Memory System implementation options. Source: Rambus

Opting for LPDDR5 would significantly simplify the system; only nine DRAM devices would be needed to provide 224 GB/s of bandwidth. LPDDR5 is potentially a useful option for a low end L3 ADAS system.

However, stepping up to L4 ADAS, bandwidth requirements rise to 300 GB/s. At this level an LPDDR5 interface running at 6.4 Gb/s would require 12 DRAM devices. This would crowd the ‘beachfront’ on the SoC with memory interfaces making layout of the SoC problematic.

GDDR6 can deliver significant design and space efficiencies over both LPDDR and DDR4. Using GDDR6, four DRAM devices can deliver 224 Gb/s, fewer than half the devices needed by LPDDR or DDR4. Therefore, GDDR6 becomes the only viable alternative at higher ADAS levels. Running at 16 Gb/s, five GDDR6 DRAM can deliver over 300 GB/s of bandwidth. The 500 GB/s needed for L5 ADAS can be comfortably passed with only eight GDDR6 DRAM devices.

GDDR6 memory meets the need for field proven robustness. It is built on tried-and-tested manufacturing processes, and offers excellent performance characteristics at a price point suited to volume manufacture. This combination of characteristics makes GDDR6 an ideal memory solution for in-vehicle AI inference.

Tackling GDDR6 design challenges

The raw performance of GDDR6 makes protecting signal integrity (SI) critical to a successful design. Maintaining SI at 1.35V at 16 Gb/s across the boundary between the analogue and digital worlds requires deep expertise; the numerous interdependencies between the behaviour of the memory and processor interfaces, package and board must be managed through co-design of these components. Failing to fully embrace co-design here is inviting extended design and simulation time or worse a costly respin.

Selecting a commercial package of silicon-proven GDDR6 IP together with design support services allows design teams to choose GDDR6 with confidence. The latest of these implementations can comfortably support the bandwidth and low-latency needs of ADAS memory processor inferencing. Choosing a GDDR6 memory subsystem comprising a co-verified PHY, digital controller, and engineering support package will cut design time and ensure optimisation of full-system signal, power integrity (SI/PI) and chip layout.

Figure 3: Example GDDR6 Memory Interface Subsystem. Source: Rambus


GDDR6 is in the memory system sweet spot for optimal ADAS designs. Its combination of bandwidth, capacity, power efficiency, reliability and price-performance are tough to beat for the majority of ADAS design scenarios.

The availability of commercial GDDR6 interface designs, verified in silicon and with full support through characterisation and debug mean designers should feel confident in selecting GDDR6 for current and future generations of ADAS design.


Frank Ferro is senior director of product marketing for IP Cores at Rambus Inc.

Related links and articles:

News articles:

GDDR6: The next-generation graphics DRAM

China’s Goodix completes acquisition of Dream Chip

Rambus to buy Inphi memory interconnect business

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles