Memory IP halves register file power consumption
Register files are usually small amounts of high-speed multi-ported SRAM memory directly adjacent to compute blocks to store interim computation results and various flags for operation of the logic. The activity level matches the logic to which they are coupled.
“Standard off-the-shelf register file IP is usually based on the foundry bit cell, and whilst this give optimal area utilisation, the power metrics are often poor – with the bit cell itself precluding a reduction in operating voltage to tune the logic for a range of performance goals,” said Tony Stansfield, Surecore’s CTO, in a statement. “Designers are forced to implement multiple power islands – at least one for the logic and one for the memories. This introduces a level of physical design complexity plus the addition of level shifters as well as necessitating considerable care with the timing analysis strategy.”
Stansfield continued: “Our register file architecture readily supports both a wide operating voltage range as well as the capability to deliver the high performance needed by AI applications.”
Surecore has previously delivered SRAM capable of wide operating voltage range. That memory is besed on the foundry bit cell together with Surecore’s Smart-Assist technology to make sure the bit cell is always operated in the foundry recommended voltage window.
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In contrast the MiniMiser architecture is based on a customised storage elements to deliver improved power characteristics even at nominal process voltages. The architecture lends itself to multiple optimisation criteria – multi-port and high-performance variants can be generated by the company’s compiler technology.
“MiniMiser gives developers a new way of optimising the power envelope for their design. Savings of over 50 percent can be delivered just by swapping in MiniMiser instances,” said Paul Wells, CEO of Surecore.
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