The partnership will look to provide a joint solution that will allow instruction set architecture (ISA) extensions to be added or changed in the field.
Extending RISC-V ISA with custom instruction set extension that are based on eFPGA co-extended core will be a key differentiator for the next processor unit’s generation. It will allow the addition of any instruction to accelerate functions in the field. This won’t break any software compatibility and it will provide space for designers to differentiate products.
Menta Chief Executive Officer Vincent Markus said, “The innovative RISC-V ISA technology is open, compact, modular and extensible, making it a perfect fit for our eFPGA product line strategy.”
The eFPGA will act as a hardware co-extended core for the RISC-V CPU. It will allow addition or reconfiguration of ISAs for a product’s life. Andes RISC-V processor families, which are now used as mainstream computing engine, will have their ACE (Andes Custom Extension) feature enhanced by eFPGA hardware support.
ACE is a framework that allows the definition of new instructions on Andes RISC-V processor cores. By writing ACE scripts for instruction semantics and concise Verilog for instruction execution RTL, SoC designers can easily use Andes COPILOT (Custom-OPtimized Instruction deveLOpment Tools) to generate all required components automatically and extend the existing Andes processor package. This includes the processor RTL, compilation tools, debugger and cycle-accurate simulator, to support the new instructions to accelerate domain specific applications.
“By cooperating with Menta, we enable a brand new usage of Andes CPU cores to the market that embraces the characteristic of extensibility for the RISC-V ecosystem, especially in applications that require space for development and differentiation including AI and 5G,” said Chief Technology Officer and Executive Vice President of Andes Technology Dr. Charlie Su. “Customers can optimize and enrich their hardware with expected scale of cost by using Menta eFPGA solution to make reconfiguration of ACE custom instruction possible in post-silicon updates.”
The delivery of Menta pre-programmed eFPGA cores combined with the Andes RISC-V CPU cores will be provided with specialized user interface tools to program the eFPGA matrix and set up the RISC-V application programmable parameters, within a complete and optimized software solution.